summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-30 18:18:11 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-13 22:18:35 -0400
commit1d9d7c04bbbaa38080c3c8f256546bd63f65d494 (patch)
treeeb130549cf93074b1d928f5cc7bd5f103678f091 /drivers/gpu/nvgpu/gk20a
parent72f6c441c80a2c697230400bf042e7b96bffca72 (diff)
gpu: nvgpu: Wait for empty always has GR enabled
Whenever wait for empty HAL is called, GR is out of reset. Check for GR being out of reset was adding an extra dependency to MC, so just remove that code. JIRA NVGPU-964 Change-Id: Ic6d607fd2e29359a67896973517d8de6542029e9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813522 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 2a871b5a..b94eade1 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -327,7 +327,6 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
327 u32 expect_delay) 327 u32 expect_delay)
328{ 328{
329 u32 delay = expect_delay; 329 u32 delay = expect_delay;
330 bool gr_enabled;
331 bool ctxsw_active; 330 bool ctxsw_active;
332 bool gr_busy; 331 bool gr_busy;
333 u32 gr_engine_id; 332 u32 gr_engine_id;
@@ -346,9 +345,6 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
346 only when gr_status is read */ 345 only when gr_status is read */
347 (void) gk20a_readl(g, gr_status_r()); 346 (void) gk20a_readl(g, gr_status_r());
348 347
349 gr_enabled = gk20a_readl(g, mc_enable_r()) &
350 mc_enable_pgraph_enabled_f();
351
352 engine_status = gk20a_readl(g, 348 engine_status = gk20a_readl(g,
353 fifo_engine_status_r(gr_engine_id)); 349 fifo_engine_status_r(gr_engine_id));
354 350
@@ -362,8 +358,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
362 gr_busy = gk20a_readl(g, gr_engine_status_r()) & 358 gr_busy = gk20a_readl(g, gr_engine_status_r()) &
363 gr_engine_status_value_busy_f(); 359 gr_engine_status_value_busy_f();
364 360
365 if (!gr_enabled || ctx_status_invalid 361 if (ctx_status_invalid || (!gr_busy && !ctxsw_active)) {
366 || (!gr_busy && !ctxsw_active)) {
367 nvgpu_log_fn(g, "done"); 362 nvgpu_log_fn(g, "done");
368 return 0; 363 return 0;
369 } 364 }