gpu: nvgpu: Changed enum gmmu_pgsz_gk20a into macros

Changed the enum gmmu_pgsz_gk20a into macros and changed all the
instances of it.

The enum gmmu_pgsz_gk20a was being used in for loops, where it was
compared with an integer. This violates MISRA rule 10.4, which only
allows arithmetic operations on operands of the same essential type
category. Changing this enum into macro will fix this violation.

JIRA NVGPU-993

Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795593
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 17 insertions, 21 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 8d6c3b70..77458917 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -120,7 +120,7 @@ int channel_gk20a_commit_va(struct channel_gk20a *c)
         nvgpu_log_fn(g, " ");
 
         g->ops.mm.init_inst_block(&c->inst_block, c->vm,
-                        c->vm->gmmu_page_sizes[gmmu_page_size_big]);
+                        c->vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]);
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 262dbb2c..5300f7dd 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -921,7 +921,7 @@ struct gpu_ops {
                                 struct nvgpu_sgt *sgt,
                                 u64 buffer_offset,
                                 u64 size,
-                                int pgsz_idx,
+                                u32 pgsz_idx,
                                 u8 kind_v,
                                 u32 ctag_offset,
                                 u32 flags,
@@ -934,7 +934,7 @@ struct gpu_ops {
                 void (*gmmu_unmap)(struct vm_gk20a *vm,
                                 u64 vaddr,
                                 u64 size,
-                                int pgsz_idx,
+                                u32 pgsz_idx,
                                 bool va_allocated,
                                 enum gk20a_mem_rw_flag rw_flag,
                                 bool sparse,
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index ee63489e..b5626035 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -158,8 +158,8 @@ static void update_gmmu_pde_locked(struct vm_gk20a *vm,
         u32 pd_offset = pd_offset_from_index(l, pd_idx);
         u32 pde_v[2] = {0, 0};
 
-        small_valid = attrs->pgsz == gmmu_page_size_small;
-        big_valid   = attrs->pgsz == gmmu_page_size_big;
+        small_valid = attrs->pgsz == GMMU_PAGE_SIZE_SMALL;
+        big_valid   = attrs->pgsz == GMMU_PAGE_SIZE_BIG;
 
         pde_v[0] = gmmu_pde_size_full_f();
         pde_v[0] |= big_valid ?
@@ -283,24 +283,22 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
         pd_write(g, pd, pd_offset + 1, pte_w[1]);
 }
 
-enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g,
-                                        const struct gk20a_mmu_level *l,
-                                        struct nvgpu_gmmu_pd *pd, u32 pd_idx)
+u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+                                struct nvgpu_gmmu_pd *pd, u32 pd_idx)
 {
         /*
          * big and small page sizes are the same
          */
-        return gmmu_page_size_small;
+        return GMMU_PAGE_SIZE_SMALL;
 }
 
-enum gmmu_pgsz_gk20a gk20a_get_pte_pgsz(struct gk20a *g,
-                                        const struct gk20a_mmu_level *l,
-                                        struct nvgpu_gmmu_pd *pd, u32 pd_idx)
+u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+                                struct nvgpu_gmmu_pd *pd, u32 pd_idx)
 {
         /*
          * return invalid
          */
-        return gmmu_nr_page_sizes;
+        return GMMU_NR_PAGE_SIZES;
 }
 
 const struct gk20a_mmu_level gk20a_mm_levels_64k[] = {
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index b99603bb..0827d355 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -139,7 +139,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
                           struct nvgpu_sgt *sgt,
                           u64 buffer_offset,
                           u64 size,
-                          int pgsz_idx,
+                          u32 pgsz_idx,
                           u8 kind_v,
                           u32 ctag_offset,
                           u32 flags,
@@ -153,7 +153,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
 void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm,
                              u64 vaddr,
                              u64 size,
-                             int pgsz_idx,
+                             u32 pgsz_idx,
                              bool va_allocated,
                              enum gk20a_mem_rw_flag rw_flag,
                              bool sparse,
@@ -178,10 +178,8 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem,
 extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
 extern const struct gk20a_mmu_level gk20a_mm_levels_128k[];
 
-enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g,
-                                        const struct gk20a_mmu_level *l,
-                                        struct nvgpu_gmmu_pd *pd, u32 pd_idx);
-enum gmmu_pgsz_gk20a gk20a_get_pte_pgsz(struct gk20a *g,
-                                        const struct gk20a_mmu_level *l,
-                                        struct nvgpu_gmmu_pd *pd, u32 pd_idx);
+u32 gk20a_get_pde_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+                                struct nvgpu_gmmu_pd *pd, u32 pd_idx);
+u32 gk20a_get_pte_pgsz(struct gk20a *g, const struct gk20a_mmu_level *l,
+                                struct nvgpu_gmmu_pd *pd, u32 pd_idx);
 #endif /* MM_GK20A_H */