gpu: nvgpu: fix indexing in locate pte function

The current code does not properly calculate the indexes within the PDE
to access the proper entry, and it has a bug in assignement of the big
page entries. This change fixes the issue by:

(1) Passing a pointer to the level structure and dereferencing the
index offset to the next level.
(2) Changing the format of the address.
(3) Ensuring big pages are only selected if their address is set.

Bug 200364599

Change-Id: I46e32560ee341d8cfc08c077282dcb5549d2a140
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1610562
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com>

2 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 3635bfc2..0b383a83 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -287,6 +287,7 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
 }
 
 enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g,
+                                        const struct gk20a_mmu_level *l,
                                         struct nvgpu_gmmu_pd *pd, u32 pd_idx)
 {
         /*
@@ -296,6 +297,7 @@ enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g,
 }
 
 enum gmmu_pgsz_gk20a gk20a_get_pte_pgsz(struct gk20a *g,
+                                        const struct gk20a_mmu_level *l,
                                         struct nvgpu_gmmu_pd *pd, u32 pd_idx)
 {
         /*
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index 2478ee1f..ee0c2a07 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -184,7 +184,9 @@ extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
 extern const struct gk20a_mmu_level gk20a_mm_levels_128k[];
 
 enum gmmu_pgsz_gk20a gk20a_get_pde_pgsz(struct gk20a *g,
+                                        const struct gk20a_mmu_level *l,
                                         struct nvgpu_gmmu_pd *pd, u32 pd_idx);
 enum gmmu_pgsz_gk20a gk20a_get_pte_pgsz(struct gk20a *g,
+                                        const struct gk20a_mmu_level *l,
                                         struct nvgpu_gmmu_pd *pd, u32 pd_idx);
 #endif /* MM_GK20A_H */