diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-29 18:00:24 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-11 13:56:06 -0400 |
commit | 19fdb429c2b04d13faecad8b2e5466e9f3c7b8c7 (patch) | |
tree | e92f6d93ae2593286546f983b9a1fff8638aa9a6 /drivers/gpu/nvgpu/gk20a | |
parent | 1a4647272f4fe50137c79583b698c1ef6f5def12 (diff) |
gpu: nvgpu: Wrappers for checking platform type
Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.
The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.
JIRA NVGPU-16
Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fence_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fence_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 17 |
10 files changed, 28 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index 3119e373..e81a5b2a 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -14,10 +14,9 @@ | |||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <soc/tegra/chip-id.h> | ||
18 | |||
19 | #include <nvgpu/page_allocator.h> | 17 | #include <nvgpu/page_allocator.h> |
20 | #include <nvgpu/log.h> | 18 | #include <nvgpu/log.h> |
19 | #include <nvgpu/soc.h> | ||
21 | 20 | ||
22 | #include "gk20a.h" | 21 | #include "gk20a.h" |
23 | 22 | ||
@@ -31,7 +30,7 @@ void gk20a_bus_init_hw(struct gk20a *g) | |||
31 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 30 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
32 | 31 | ||
33 | /* enable pri timeout only on silicon */ | 32 | /* enable pri timeout only on silicon */ |
34 | if (tegra_platform_is_silicon()) { | 33 | if (nvgpu_platform_is_silicon(g)) { |
35 | gk20a_writel(g, | 34 | gk20a_writel(g, |
36 | timer_pri_timeout_r(), | 35 | timer_pri_timeout_r(), |
37 | timer_pri_timeout_period_f( | 36 | timer_pri_timeout_period_f( |
@@ -46,7 +45,7 @@ void gk20a_bus_init_hw(struct gk20a *g) | |||
46 | timer_pri_timeout_en_en_disabled_f()); | 45 | timer_pri_timeout_en_en_disabled_f()); |
47 | } | 46 | } |
48 | 47 | ||
49 | if (!tegra_platform_is_silicon()) | 48 | if (!nvgpu_platform_is_silicon(g)) |
50 | gk20a_writel(g, bus_intr_en_0_r(), 0x0); | 49 | gk20a_writel(g, bus_intr_en_0_r(), 0x0); |
51 | else | 50 | else |
52 | gk20a_writel(g, bus_intr_en_0_r(), | 51 | gk20a_writel(g, bus_intr_en_0_r(), |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index c502add5..5b27953e 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -618,7 +618,8 @@ int gk20a_ce_execute_ops(struct device *dev, | |||
618 | memcpy((void *)&ce_cmd_buf_fence_in, | 618 | memcpy((void *)&ce_cmd_buf_fence_in, |
619 | (void *)(cmd_buf_cpu_va + fence_index), | 619 | (void *)(cmd_buf_cpu_va + fence_index), |
620 | sizeof(struct gk20a_fence *)); | 620 | sizeof(struct gk20a_fence *)); |
621 | ret = gk20a_fence_wait(ce_cmd_buf_fence_in, gk20a_get_gr_idle_timeout(g)); | 621 | ret = gk20a_fence_wait(g, ce_cmd_buf_fence_in, |
622 | gk20a_get_gr_idle_timeout(g)); | ||
622 | 623 | ||
623 | gk20a_fence_put(ce_cmd_buf_fence_in); | 624 | gk20a_fence_put(ce_cmd_buf_fence_in); |
624 | /* Reset the stored last pre-sync */ | 625 | /* Reset the stored last pre-sync */ |
@@ -645,7 +646,8 @@ int gk20a_ce_execute_ops(struct device *dev, | |||
645 | if (methodSize) { | 646 | if (methodSize) { |
646 | /* TODO: Remove CPU pre-fence wait */ | 647 | /* TODO: Remove CPU pre-fence wait */ |
647 | if (gk20a_fence_in) { | 648 | if (gk20a_fence_in) { |
648 | ret = gk20a_fence_wait(gk20a_fence_in, gk20a_get_gr_idle_timeout(g)); | 649 | ret = gk20a_fence_wait(g, gk20a_fence_in, |
650 | gk20a_get_gr_idle_timeout(g)); | ||
649 | gk20a_fence_put(gk20a_fence_in); | 651 | gk20a_fence_put(gk20a_fence_in); |
650 | if (ret) | 652 | if (ret) |
651 | goto noop; | 653 | goto noop; |
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 443cd5e1..baffed46 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include "gk20a.h" | 25 | #include "gk20a.h" |
26 | 26 | ||
27 | #include <nvgpu/log.h> | 27 | #include <nvgpu/log.h> |
28 | #include <nvgpu/soc.h> | ||
28 | 29 | ||
29 | #include <nvgpu/hw/gk20a/hw_trim_gk20a.h> | 30 | #include <nvgpu/hw/gk20a/hw_trim_gk20a.h> |
30 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> | 31 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> |
@@ -268,7 +269,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
268 | 269 | ||
269 | gk20a_dbg_fn(""); | 270 | gk20a_dbg_fn(""); |
270 | 271 | ||
271 | if (!tegra_platform_is_silicon()) | 272 | if (!nvgpu_platform_is_silicon(g)) |
272 | return 0; | 273 | return 0; |
273 | 274 | ||
274 | /* get old coefficients */ | 275 | /* get old coefficients */ |
diff --git a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c index a5aeae08..c886101c 100644 --- a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #include <nvgpu/semaphore.h> | 20 | #include <nvgpu/semaphore.h> |
21 | #include <nvgpu/kmem.h> | 21 | #include <nvgpu/kmem.h> |
22 | #include <nvgpu/soc.h> | ||
22 | 23 | ||
23 | #include "gk20a.h" | 24 | #include "gk20a.h" |
24 | #include "channel_gk20a.h" | 25 | #include "channel_gk20a.h" |
@@ -80,10 +81,10 @@ static inline bool gk20a_fence_is_valid(struct gk20a_fence *f) | |||
80 | return valid; | 81 | return valid; |
81 | } | 82 | } |
82 | 83 | ||
83 | int gk20a_fence_wait(struct gk20a_fence *f, int timeout) | 84 | int gk20a_fence_wait(struct gk20a *g, struct gk20a_fence *f, int timeout) |
84 | { | 85 | { |
85 | if (f && gk20a_fence_is_valid(f)) { | 86 | if (f && gk20a_fence_is_valid(f)) { |
86 | if (!tegra_platform_is_silicon()) | 87 | if (!nvgpu_platform_is_silicon(g)) |
87 | timeout = (u32)MAX_SCHEDULE_TIMEOUT; | 88 | timeout = (u32)MAX_SCHEDULE_TIMEOUT; |
88 | return f->ops->wait(f, timeout); | 89 | return f->ops->wait(f, timeout); |
89 | } | 90 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fence_gk20a.h b/drivers/gpu/nvgpu/gk20a/fence_gk20a.h index 426556cc..77dae9a7 100644 --- a/drivers/gpu/nvgpu/gk20a/fence_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fence_gk20a.h | |||
@@ -25,6 +25,7 @@ struct sync_timeline; | |||
25 | struct sync_fence; | 25 | struct sync_fence; |
26 | struct nvgpu_semaphore; | 26 | struct nvgpu_semaphore; |
27 | struct channel_gk20a; | 27 | struct channel_gk20a; |
28 | struct gk20a; | ||
28 | 29 | ||
29 | struct gk20a_fence_ops; | 30 | struct gk20a_fence_ops; |
30 | 31 | ||
@@ -83,7 +84,7 @@ void gk20a_init_fence(struct gk20a_fence *f, | |||
83 | /* Fence operations */ | 84 | /* Fence operations */ |
84 | void gk20a_fence_put(struct gk20a_fence *f); | 85 | void gk20a_fence_put(struct gk20a_fence *f); |
85 | struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f); | 86 | struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f); |
86 | int gk20a_fence_wait(struct gk20a_fence *f, int timeout); | 87 | int gk20a_fence_wait(struct gk20a *g, struct gk20a_fence *f, int timeout); |
87 | bool gk20a_fence_is_expired(struct gk20a_fence *f); | 88 | bool gk20a_fence_is_expired(struct gk20a_fence *f); |
88 | int gk20a_fence_install_fd(struct gk20a_fence *f); | 89 | int gk20a_fence_install_fd(struct gk20a_fence *f); |
89 | 90 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index c7db67fe..bdd068fe 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <nvgpu/semaphore.h> | 31 | #include <nvgpu/semaphore.h> |
32 | #include <nvgpu/kmem.h> | 32 | #include <nvgpu/kmem.h> |
33 | #include <nvgpu/log.h> | 33 | #include <nvgpu/log.h> |
34 | #include <nvgpu/soc.h> | ||
34 | 35 | ||
35 | #include "gk20a.h" | 36 | #include "gk20a.h" |
36 | #include "debug_gk20a.h" | 37 | #include "debug_gk20a.h" |
@@ -3349,7 +3350,7 @@ static void gk20a_fifo_apply_pb_timeout(struct gk20a *g) | |||
3349 | { | 3350 | { |
3350 | u32 timeout; | 3351 | u32 timeout; |
3351 | 3352 | ||
3352 | if (tegra_platform_is_silicon()) { | 3353 | if (nvgpu_platform_is_silicon(g)) { |
3353 | timeout = gk20a_readl(g, fifo_pb_timeout_r()); | 3354 | timeout = gk20a_readl(g, fifo_pb_timeout_r()); |
3354 | timeout &= ~fifo_pb_timeout_detection_enabled_f(); | 3355 | timeout &= ~fifo_pb_timeout_detection_enabled_f(); |
3355 | gk20a_writel(g, fifo_pb_timeout_r(), timeout); | 3356 | gk20a_writel(g, fifo_pb_timeout_r(), timeout); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 5fc57494..339656c7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -43,6 +43,7 @@ | |||
43 | #include <nvgpu/kmem.h> | 43 | #include <nvgpu/kmem.h> |
44 | #include <nvgpu/allocator.h> | 44 | #include <nvgpu/allocator.h> |
45 | #include <nvgpu/timers.h> | 45 | #include <nvgpu/timers.h> |
46 | #include <nvgpu/soc.h> | ||
46 | 47 | ||
47 | #include "gk20a.h" | 48 | #include "gk20a.h" |
48 | #include "debug_gk20a.h" | 49 | #include "debug_gk20a.h" |
@@ -295,7 +296,7 @@ static int gk20a_init_support(struct platform_device *dev) | |||
295 | goto fail; | 296 | goto fail; |
296 | } | 297 | } |
297 | 298 | ||
298 | if (tegra_cpu_is_asim()) { | 299 | if (nvgpu_platform_is_simulation(g)) { |
299 | err = gk20a_init_sim_support(dev); | 300 | err = gk20a_init_sim_support(dev); |
300 | if (err) | 301 | if (err) |
301 | goto fail; | 302 | goto fail; |
@@ -954,9 +955,6 @@ static int gk20a_probe(struct platform_device *dev) | |||
954 | return -ENODATA; | 955 | return -ENODATA; |
955 | } | 956 | } |
956 | 957 | ||
957 | if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) | ||
958 | platform->is_fmodel = true; | ||
959 | |||
960 | gk20a_dbg_fn(""); | 958 | gk20a_dbg_fn(""); |
961 | 959 | ||
962 | platform_set_drvdata(dev, platform); | 960 | platform_set_drvdata(dev, platform); |
@@ -973,6 +971,9 @@ static int gk20a_probe(struct platform_device *dev) | |||
973 | set_gk20a(dev, gk20a); | 971 | set_gk20a(dev, gk20a); |
974 | gk20a->dev = &dev->dev; | 972 | gk20a->dev = &dev->dev; |
975 | 973 | ||
974 | if (nvgpu_platform_is_simulation(gk20a)) | ||
975 | platform->is_fmodel = true; | ||
976 | |||
976 | nvgpu_kmem_init(gk20a); | 977 | nvgpu_kmem_init(gk20a); |
977 | 978 | ||
978 | gk20a->irq_stall = platform_get_irq(dev, 0); | 979 | gk20a->irq_stall = platform_get_irq(dev, 0); |
@@ -1030,7 +1031,7 @@ static int gk20a_probe(struct platform_device *dev) | |||
1030 | return err; | 1031 | return err; |
1031 | } | 1032 | } |
1032 | 1033 | ||
1033 | gk20a->mm.has_physical_mode = !is_tegra_hypervisor_mode(); | 1034 | gk20a->mm.has_physical_mode = !nvgpu_is_hypervisor_mode(gk20a); |
1034 | 1035 | ||
1035 | return 0; | 1036 | return 0; |
1036 | } | 1037 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 9d931520..1cff8dd5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -34,7 +34,6 @@ struct dbg_profiler_object_data; | |||
34 | #include <nvgpu/lock.h> | 34 | #include <nvgpu/lock.h> |
35 | #include <linux/nvgpu.h> | 35 | #include <linux/nvgpu.h> |
36 | #include <linux/irqreturn.h> | 36 | #include <linux/irqreturn.h> |
37 | #include <soc/tegra/chip-id.h> | ||
38 | #include <linux/version.h> | 37 | #include <linux/version.h> |
39 | #include <linux/atomic.h> | 38 | #include <linux/atomic.h> |
40 | #include <linux/cdev.h> | 39 | #include <linux/cdev.h> |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 78332ee7..7472c7cd 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -569,7 +569,7 @@ static int gk20a_vidmem_clear_all(struct gk20a *g) | |||
569 | NVGPU_TIMER_CPU_TIMER); | 569 | NVGPU_TIMER_CPU_TIMER); |
570 | 570 | ||
571 | do { | 571 | do { |
572 | err = gk20a_fence_wait(gk20a_fence_out, | 572 | err = gk20a_fence_wait(g, gk20a_fence_out, |
573 | gk20a_get_gr_idle_timeout(g)); | 573 | gk20a_get_gr_idle_timeout(g)); |
574 | } while (err == -ERESTARTSYS && | 574 | } while (err == -ERESTARTSYS && |
575 | !nvgpu_timeout_expired(&timeout)); | 575 | !nvgpu_timeout_expired(&timeout)); |
@@ -2560,7 +2560,7 @@ static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct nvgpu_mem *mem) | |||
2560 | NVGPU_TIMER_CPU_TIMER); | 2560 | NVGPU_TIMER_CPU_TIMER); |
2561 | 2561 | ||
2562 | do { | 2562 | do { |
2563 | err = gk20a_fence_wait(gk20a_last_fence, | 2563 | err = gk20a_fence_wait(g, gk20a_last_fence, |
2564 | gk20a_get_gr_idle_timeout(g)); | 2564 | gk20a_get_gr_idle_timeout(g)); |
2565 | } while (err == -ERESTARTSYS && | 2565 | } while (err == -ERESTARTSYS && |
2566 | !nvgpu_timeout_expired(&timeout)); | 2566 | !nvgpu_timeout_expired(&timeout)); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 38b8da9c..7df0c71c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -3642,19 +3642,10 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
3642 | 3642 | ||
3643 | gk20a_dbg_fn(""); | 3643 | gk20a_dbg_fn(""); |
3644 | 3644 | ||
3645 | if (tegra_cpu_is_asim()) { | 3645 | gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), |
3646 | /* TBD: calculate threshold for silicon */ | 3646 | PMU_PG_IDLE_THRESHOLD); |
3647 | gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), | 3647 | gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id), |
3648 | PMU_PG_IDLE_THRESHOLD_SIM); | 3648 | PMU_PG_POST_POWERUP_IDLE_THRESHOLD); |
3649 | gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id), | ||
3650 | PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM); | ||
3651 | } else { | ||
3652 | /* TBD: calculate threshold for silicon */ | ||
3653 | gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), | ||
3654 | PMU_PG_IDLE_THRESHOLD); | ||
3655 | gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id), | ||
3656 | PMU_PG_POST_POWERUP_IDLE_THRESHOLD); | ||
3657 | } | ||
3658 | 3649 | ||
3659 | if (g->ops.pmu.pmu_pg_init_param) | 3650 | if (g->ops.pmu.pmu_pg_init_param) |
3660 | g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); | 3651 | g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); |