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authorDeepak Nibade <dnibade@nvidia.com>2018-04-06 09:04:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-10 14:23:07 -0400
commit19aa748be53787da6abe435ea7043a7827d0fde0 (patch)
treed4588653f031bb0ca4410e287ce0ef291e455422 /drivers/gpu/nvgpu/gk20a
parent4314771142e0b68810b8fa86ec45b6f6b4e24651 (diff)
gpu: nvgpu: add support to get unicast addresses on volta
We have new broadcast registers on Volta, and we need to generate correct unicast addresses for them so that we can write those registers to context image Add new GR HAL create_priv_addr_table() to do this conversion Set gr_gk20a_create_priv_addr_table() for older chips Set gr_gv11b_create_priv_addr_table() for Volta gr_gv11b_create_priv_addr_table() will use the broadcast flags and then generate appriate list of unicast register for each broadcast register Bug 200398811 Jira NVGPU-556 Change-Id: Id53a9e56106d200fe560ffc93394cc0e976f455f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690027 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c10
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h7
3 files changed, 17 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 164668cb..edc1c5ff 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -466,6 +466,10 @@ struct gpu_ops {
466 u32 *gpc_num, u32 *tpc_num, 466 u32 *gpc_num, u32 *tpc_num,
467 u32 *ppc_num, u32 *be_num, 467 u32 *ppc_num, u32 *be_num,
468 u32 *broadcast_flags); 468 u32 *broadcast_flags);
469 int (*create_priv_addr_table)(struct gk20a *g,
470 u32 addr,
471 u32 *priv_addr_table,
472 u32 *num_registers);
469 } gr; 473 } gr;
470 struct { 474 struct {
471 void (*init_hw)(struct gk20a *g); 475 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 3912a1df..04d00e55 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6325,7 +6325,7 @@ int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
6325 return -EINVAL; 6325 return -EINVAL;
6326} 6326}
6327 6327
6328static int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr, 6328int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr,
6329 u32 gpc_num, 6329 u32 gpc_num,
6330 u32 *priv_addr_table, u32 *t) 6330 u32 *priv_addr_table, u32 *t)
6331{ 6331{
@@ -6347,7 +6347,7 @@ static int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr,
6347 * GPC/TPC addresses. The addresses generated by this function can be 6347 * GPC/TPC addresses. The addresses generated by this function can be
6348 * successfully processed by gr_gk20a_find_priv_offset_in_buffer 6348 * successfully processed by gr_gk20a_find_priv_offset_in_buffer
6349 */ 6349 */
6350static int gr_gk20a_create_priv_addr_table(struct gk20a *g, 6350int gr_gk20a_create_priv_addr_table(struct gk20a *g,
6351 u32 addr, 6351 u32 addr,
6352 u32 *priv_addr_table, 6352 u32 *priv_addr_table,
6353 u32 *num_registers) 6353 u32 *num_registers)
@@ -6494,7 +6494,8 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
6494 memset(offset_addrs, 0, sizeof(u32) * max_offsets); 6494 memset(offset_addrs, 0, sizeof(u32) * max_offsets);
6495 *num_offsets = 0; 6495 *num_offsets = 0;
6496 6496
6497 gr_gk20a_create_priv_addr_table(g, addr, &priv_registers[0], &num_registers); 6497 g->ops.gr.create_priv_addr_table(g, addr, &priv_registers[0],
6498 &num_registers);
6498 6499
6499 if ((max_offsets > 1) && (num_registers > max_offsets)) { 6500 if ((max_offsets > 1) && (num_registers > max_offsets)) {
6500 gk20a_dbg_fn("max_offsets = %d, num_registers = %d", 6501 gk20a_dbg_fn("max_offsets = %d, num_registers = %d",
@@ -6571,7 +6572,8 @@ int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g,
6571 memset(offset_addrs, 0, sizeof(u32) * max_offsets); 6572 memset(offset_addrs, 0, sizeof(u32) * max_offsets);
6572 *num_offsets = 0; 6573 *num_offsets = 0;
6573 6574
6574 gr_gk20a_create_priv_addr_table(g, addr, priv_registers, &num_registers); 6575 g->ops.gr.create_priv_addr_table(g, addr, priv_registers,
6576 &num_registers);
6575 6577
6576 if ((max_offsets > 1) && (num_registers > max_offsets)) { 6578 if ((max_offsets > 1) && (num_registers > max_offsets)) {
6577 err = -EINVAL; 6579 err = -EINVAL;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index ee76148a..cd58cfa3 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -825,4 +825,11 @@ int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
825 int *addr_type, 825 int *addr_type,
826 u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, 826 u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
827 u32 *broadcast_flags); 827 u32 *broadcast_flags);
828int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr,
829 u32 gpc_num,
830 u32 *priv_addr_table, u32 *t);
831int gr_gk20a_create_priv_addr_table(struct gk20a *g,
832 u32 addr,
833 u32 *priv_addr_table,
834 u32 *num_registers);
828#endif /*__GR_GK20A_H__*/ 835#endif /*__GR_GK20A_H__*/