diff options
author | Arto Merilainen <amerilainen@nvidia.com> | 2014-03-05 10:34:07 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:09:05 -0400 |
commit | 177e4e4735b1e7e5f40beab2ac74f020c3a64d86 (patch) | |
tree | 713a1a82990c0cccadc291e2aa66b723005a6f5b /drivers/gpu/nvgpu/gk20a | |
parent | ba03fd69dd0f06f499c8f069660b463c5bea1bf3 (diff) |
gpu: nvgpu: Store gpu config
This patch adds necessary code to store the gpu configuration into
gr structure.
Bug 1409151
Change-Id: I045b21ebdc849833380a3d953d951f8352842ac7
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 7eb2923a..b25782ca 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -207,6 +207,10 @@ struct gr_gk20a { | |||
207 | int initialized; | 207 | int initialized; |
208 | u32 num_fbps; | 208 | u32 num_fbps; |
209 | 209 | ||
210 | u32 comptags_per_cacheline; | ||
211 | u32 slices_per_fbp; | ||
212 | u32 cacheline_size; | ||
213 | |||
210 | u32 max_gpc_count; | 214 | u32 max_gpc_count; |
211 | u32 max_fbps_count; | 215 | u32 max_fbps_count; |
212 | u32 max_tpc_per_gpc_count; | 216 | u32 max_tpc_per_gpc_count; |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index 6da5adb9..8450f664 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -101,6 +101,10 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
101 | max_comptag_lines - 1, /* length*/ | 101 | max_comptag_lines - 1, /* length*/ |
102 | 1); /* align */ | 102 | 1); /* align */ |
103 | 103 | ||
104 | gr->comptags_per_cacheline = comptags_per_cacheline; | ||
105 | gr->slices_per_fbp = slices_per_fbp; | ||
106 | gr->cacheline_size = cacheline_size; | ||
107 | |||
104 | return 0; | 108 | return 0; |
105 | } | 109 | } |
106 | 110 | ||