gpu: nvgpu: mask intr before gpu power off

once gpu is powered off i.e. power_on set to false, nvgpu isr
does not handle stall/nonstall irq. Depending upon state
of gpu, this can result in either of following errors:

1) irq 458: nobody cared (try booting with the "irqpoll" option)
2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is
not in time.

Fix these by masking all interrupts just before gpu power off
as nvgpu won't be handling any irq anymore.

While masking interrupts, if there are any pending interrupts,
then report those with a log message.

Bug 1987855
Bug 200424832

Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770802
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 41 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index ed48253f..c8b094cf 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -93,6 +93,17 @@ int gk20a_detect_chip(struct gk20a *g)
         return gpu_init_hal(g);
 }
 
+static void gk20a_mask_interrupts(struct gk20a *g)
+{
+        if (g->ops.mc.intr_mask != NULL) {
+                g->ops.mc.intr_mask(g);
+        }
+
+        if (g->ops.mc.log_pending_intrs != NULL) {
+                g->ops.mc.log_pending_intrs(g);
+        }
+}
+
 int gk20a_prepare_poweroff(struct gk20a *g)
 {
         int ret = 0;
@@ -122,6 +133,8 @@ int gk20a_prepare_poweroff(struct gk20a *g)
         if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE))
                 gk20a_deinit_pstate_support(g);
 
+        gk20a_mask_interrupts(g);
+
         g->power_on = false;
 
         return ret;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 6d19d8a3..13c8928f 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1119,6 +1119,7 @@ struct gpu_ops {
                 int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
         } regops;
         struct {
+                void (*intr_mask)(struct gk20a *g);
                 void (*intr_enable)(struct gk20a *g);
                 void (*intr_unit_config)(struct gk20a *g,
                                 bool enable, bool is_stalling, u32 unit);
@@ -1139,6 +1140,7 @@ struct gpu_ops {
                 void (*reset)(struct gk20a *g, u32 units);
                 u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
                 bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
+                void (*log_pending_intrs)(struct gk20a *g);
         } mc;
         struct {
                 void (*show_dump)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index 9ee24ed0..26084bd6 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -121,6 +121,14 @@ u32 mc_gk20a_isr_nonstall(struct gk20a *g)
         return ops;
 }
 
+void mc_gk20a_intr_mask(struct gk20a *g)
+{
+        nvgpu_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_disabled_f());
+        nvgpu_writel(g, mc_intr_en_1_r(),
+                mc_intr_en_1_inta_disabled_f());
+}
+
 void mc_gk20a_intr_enable(struct gk20a *g)
 {
         u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
@@ -292,6 +300,21 @@ bool mc_gk20a_is_intr1_pending(struct gk20a *g,
         return is_pending;
 }
 
+void mc_gk20a_log_pending_intrs(struct gk20a *g)
+{
+        u32 intr;
+
+        intr = g->ops.mc.intr_stall(g);
+        if (intr != 0U) {
+                nvgpu_info(g, "Pending stall intr0=0x%08x", intr);
+        }
+
+        intr = g->ops.mc.intr_nonstall(g);
+        if (intr != 0U) {
+                nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr);
+        }
+}
+
 void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops)
 {
         bool semaphore_wakeup, post_events;
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
index 1b59d634..0dfdf906 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
@@ -24,6 +24,7 @@
 #define MC_GK20A_H
 struct gk20a;
 
+void mc_gk20a_intr_mask(struct gk20a *g);
 void mc_gk20a_intr_enable(struct gk20a *g);
 void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
                 bool is_stalling, u32 mask);
@@ -41,5 +42,7 @@ void gk20a_mc_reset(struct gk20a *g, u32 units);
 u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
 bool mc_gk20a_is_intr1_pending(struct gk20a *g,
                 enum nvgpu_unit unit, u32 mc_intr_1);
+void mc_gk20a_log_pending_intrs(struct gk20a *g);
 void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops);
+
 #endif /* MC_GK20A_H */