diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-20 17:08:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-21 02:11:31 -0400 |
commit | 13bebeced17c206995bd17c573d094968cc0fbca (patch) | |
tree | 3892a00b5d083ad96dbe2ddbf7a9386c14afe660 /drivers/gpu/nvgpu/gk20a | |
parent | e32f62fadfcde413bcd9b5af61ad884e27ba2bf1 (diff) |
gpu: nvgpu: Use retry timer for short delays
CPU timer is inaccurate for short delays, and can produce false
timeouts.
Bug 1903521
Change-Id: I688b5a59489b62cbd59e418d641fd188ecd3b7e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467002
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 9 |
2 files changed, 17 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f47d3b12..57cd266d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1596,8 +1596,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1596 | if (!g->is_fmodel) { | 1596 | if (!g->is_fmodel) { |
1597 | struct nvgpu_timeout timeout; | 1597 | struct nvgpu_timeout timeout; |
1598 | 1598 | ||
1599 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | 1599 | nvgpu_timeout_init(g, &timeout, |
1600 | NVGPU_TIMER_CPU_TIMER); | 1600 | FE_PWR_MODE_TIMEOUT_MAX / |
1601 | FE_PWR_MODE_TIMEOUT_DEFAULT, | ||
1602 | NVGPU_TIMER_RETRY_TIMER); | ||
1601 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1603 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1602 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); | 1604 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); |
1603 | do { | 1605 | do { |
@@ -1639,8 +1641,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1639 | if (!g->is_fmodel) { | 1641 | if (!g->is_fmodel) { |
1640 | struct nvgpu_timeout timeout; | 1642 | struct nvgpu_timeout timeout; |
1641 | 1643 | ||
1642 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | 1644 | nvgpu_timeout_init(g, &timeout, |
1643 | NVGPU_TIMER_CPU_TIMER); | 1645 | FE_PWR_MODE_TIMEOUT_MAX / |
1646 | FE_PWR_MODE_TIMEOUT_DEFAULT, | ||
1647 | NVGPU_TIMER_RETRY_TIMER); | ||
1644 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1648 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1645 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); | 1649 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); |
1646 | 1650 | ||
@@ -4998,8 +5002,10 @@ static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) | |||
4998 | 5002 | ||
4999 | gk20a_dbg_fn(""); | 5003 | gk20a_dbg_fn(""); |
5000 | 5004 | ||
5001 | nvgpu_timeout_init(g, &timeout, CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / 1000, | 5005 | nvgpu_timeout_init(g, &timeout, |
5002 | NVGPU_TIMER_CPU_TIMER); | 5006 | CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / |
5007 | CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT, | ||
5008 | NVGPU_TIMER_RETRY_TIMER); | ||
5003 | do { | 5009 | do { |
5004 | fecs_scrubbing = gk20a_readl(g, gr_fecs_dmactl_r()) & | 5010 | fecs_scrubbing = gk20a_readl(g, gr_fecs_dmactl_r()) & |
5005 | (gr_fecs_dmactl_imem_scrubbing_m() | | 5011 | (gr_fecs_dmactl_imem_scrubbing_m() | |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 257d9f7c..229d5b4f 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" | 42 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" |
43 | 43 | ||
44 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 2000 | 44 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 |
45 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | 45 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 |
46 | 46 | ||
47 | #define gk20a_dbg_pmu(fmt, arg...) \ | 47 | #define gk20a_dbg_pmu(fmt, arg...) \ |
@@ -2315,7 +2315,7 @@ int pmu_idle(struct pmu_gk20a *pmu) | |||
2315 | struct nvgpu_timeout timeout; | 2315 | struct nvgpu_timeout timeout; |
2316 | u32 idle_stat; | 2316 | u32 idle_stat; |
2317 | 2317 | ||
2318 | nvgpu_timeout_init(g, &timeout, 2000, NVGPU_TIMER_CPU_TIMER); | 2318 | nvgpu_timeout_init(g, &timeout, 2000, NVGPU_TIMER_RETRY_TIMER); |
2319 | 2319 | ||
2320 | /* wait for pmu idle */ | 2320 | /* wait for pmu idle */ |
2321 | do { | 2321 | do { |
@@ -2418,8 +2418,9 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2418 | g->blcg_enabled); | 2418 | g->blcg_enabled); |
2419 | 2419 | ||
2420 | nvgpu_timeout_init(g, &timeout, | 2420 | nvgpu_timeout_init(g, &timeout, |
2421 | PMU_MEM_SCRUBBING_TIMEOUT_MAX / 1000, | 2421 | PMU_MEM_SCRUBBING_TIMEOUT_MAX / |
2422 | NVGPU_TIMER_CPU_TIMER); | 2422 | PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT, |
2423 | NVGPU_TIMER_RETRY_TIMER); | ||
2423 | do { | 2424 | do { |
2424 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & | 2425 | u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & |
2425 | (pwr_falcon_dmactl_dmem_scrubbing_m() | | 2426 | (pwr_falcon_dmactl_dmem_scrubbing_m() | |