gpu: nvgpu: Fix nvgpu_readl MISRA 17.7 violations

MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_readl.

JIRA NVGPU-677

Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807528
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 7 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 91ffbb7e..a40d93fd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -345,7 +345,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
         do {
                 /* fmodel: host gets fifo_engine_status(gr) from gr
                    only when gr_status is read */
-                gk20a_readl(g, gr_status_r());
+                (void) gk20a_readl(g, gr_status_r());
 
                 gr_enabled = gk20a_readl(g, mc_enable_r()) &
                         mc_enable_pgraph_enabled_f();
@@ -1482,7 +1482,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
                         gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() |
                         gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() |
                         gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f());
-        gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+        (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
         nvgpu_udelay(10);
 
         gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
@@ -1495,7 +1495,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
                         gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() |
                         gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() |
                         gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f());
-        gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+        (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
         nvgpu_udelay(10);
 
         if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index f7631a9c..f9996e71 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -172,7 +172,7 @@ void mc_gk20a_intr_stall_pause(struct gk20a *g)
                 mc_intr_en_0_inta_disabled_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_0_r());
+        (void) gk20a_readl(g, mc_intr_en_0_r());
 }
 
 void mc_gk20a_intr_stall_resume(struct gk20a *g)
@@ -181,7 +181,7 @@ void mc_gk20a_intr_stall_resume(struct gk20a *g)
                 mc_intr_en_0_inta_hardware_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_0_r());
+        (void) gk20a_readl(g, mc_intr_en_0_r());
 }
 
 void mc_gk20a_intr_nonstall_pause(struct gk20a *g)
@@ -190,7 +190,7 @@ void mc_gk20a_intr_nonstall_pause(struct gk20a *g)
                 mc_intr_en_0_inta_disabled_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_1_r());
+        (void) gk20a_readl(g, mc_intr_en_1_r());
 }
 
 void mc_gk20a_intr_nonstall_resume(struct gk20a *g)
@@ -199,7 +199,7 @@ void mc_gk20a_intr_nonstall_resume(struct gk20a *g)
                 mc_intr_en_0_inta_hardware_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_1_r());
+        (void) gk20a_readl(g, mc_intr_en_1_r());
 }
 
 u32 mc_gk20a_intr_stall(struct gk20a *g)