gpu: nvgpu: clear all handled fifo interrupts

Issue is that local variable clear_intr is reset if fifo intr
handler happens to handle interrupts handled by fifo_error_isr.
This fix is to take care of clearing all handled fifo interrupts.

Bug 2361571

Change-Id: Ic8fe2294cfb25c58925942750a81c104ec9747de
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1960330
(cherry picked from commit 1195239d1c624e600ec4152374c493e887a90774
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/1979744
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 3632963a..2e19d585 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2820,8 +2820,8 @@ void gk20a_fifo_isr(struct gk20a *g)
                         g->ops.fifo.handle_ctxsw_timeout(g, fifo_intr);
                 }
 
-                if (unlikely(fifo_intr & error_intr_mask)) {
-                        clear_intr = fifo_error_isr(g, fifo_intr);
+                if (unlikely((fifo_intr & error_intr_mask) != 0U)) {
+                        clear_intr |= fifo_error_isr(g, fifo_intr);
                 }
 
                 nvgpu_mutex_release(&g->fifo.intr.isr.mutex);