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authorSeema Khowala <seemaj@nvidia.com>2018-05-07 15:06:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-06-24 12:53:33 -0400
commit067ddbc4e4df3f1f756f03e7865c369a46f420aa (patch)
treec3de983f555152fedc3df2107bbae414bd119351 /drivers/gpu/nvgpu/gk20a
parent3eede64de058fcb1e39d723dd146bcd5d06c6f43 (diff)
gpu: nvgpu: remove timeout_rc_type i/p param
-is_preempt_pending hal does not need timeout_rc_type input param as for volta, reset_eng_bitmask is saved if preempt times out. For legacy chips, recovery triggers mmu fault and mmu fault handler takes care of resetting engines. -For volta, no special input param needed to differentiate between preempt polling during normal scenario and preempt polling during recovery. Recovery path uses preempt_ch_tsg hal to issue preempt. This hal does not issue recovery if preempt times out. Bug 2125776 Bug 2108544 Bug 2105322 Bug 2092051 Bug 2048824 Bug 2043838 Bug 2039587 Bug 2028993 Bug 2029245 Bug 2065990 Bug 1945121 Bug 200401707 Bug 200393631 Bug 200327596 Change-Id: Ie76a18ae0be880cfbeee615859a08179fb974fa8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709799 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c9
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.h7
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h4
3 files changed, 8 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 00119300..c8789c3a 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2704,7 +2704,7 @@ void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg)
2704} 2704}
2705 2705
2706int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, 2706int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
2707 unsigned int id_type, unsigned int timeout_rc_type) 2707 unsigned int id_type)
2708{ 2708{
2709 struct nvgpu_timeout timeout; 2709 struct nvgpu_timeout timeout;
2710 u32 delay = GR_IDLE_CHECK_DEFAULT; 2710 u32 delay = GR_IDLE_CHECK_DEFAULT;
@@ -2777,8 +2777,8 @@ int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg)
2777 id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL; 2777 id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL;
2778 2778
2779 /* wait for preempt */ 2779 /* wait for preempt */
2780 ret = g->ops.fifo.is_preempt_pending(g, id, id_type, 2780 ret = g->ops.fifo.is_preempt_pending(g, id, id_type);
2781 PREEMPT_TIMEOUT_RC); 2781
2782 return ret; 2782 return ret;
2783} 2783}
2784 2784
@@ -3448,8 +3448,7 @@ static int __locked_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
3448 gk20a_readl(g, fifo_preempt_r())); 3448 gk20a_readl(g, fifo_preempt_r()));
3449#endif 3449#endif
3450 if (wait_preempt) { 3450 if (wait_preempt) {
3451 g->ops.fifo.is_preempt_pending( 3451 g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type);
3452 g, preempt_id, preempt_type, PREEMPT_TIMEOUT_RC);
3453 } 3452 }
3454#ifdef TRACEPOINTS_ENABLED 3453#ifdef TRACEPOINTS_ENABLED
3455 trace_gk20a_reschedule_preempted_next(ch->chid); 3454 trace_gk20a_reschedule_preempted_next(ch->chid);
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index bccd15f6..d6e759ac 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -50,9 +50,6 @@ enum {
50#define ID_TYPE_TSG 1 50#define ID_TYPE_TSG 1
51#define ID_TYPE_UNKNOWN ((u32)~0) 51#define ID_TYPE_UNKNOWN ((u32)~0)
52 52
53#define PREEMPT_TIMEOUT_RC 1
54#define PREEMPT_TIMEOUT_NORC 0
55
56#define RC_YES 1 53#define RC_YES 1
57#define RC_NO 0 54#define RC_NO 0
58 55
@@ -390,8 +387,8 @@ void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a);
390 387
391u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g); 388u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g);
392 389
393int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, 390int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
394 unsigned int timeout_rc_type); 391 unsigned int id_type);
395int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg); 392int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg);
396void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, 393void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, u32 id,
397 unsigned int id_type); 394 unsigned int id_type);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 25146b8b..fac02f68 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -662,9 +662,9 @@ struct gpu_ops {
662 struct ch_state *ch_state); 662 struct ch_state *ch_state);
663 u32 (*intr_0_error_mask)(struct gk20a *g); 663 u32 (*intr_0_error_mask)(struct gk20a *g);
664 int (*is_preempt_pending)(struct gk20a *g, u32 id, 664 int (*is_preempt_pending)(struct gk20a *g, u32 id,
665 unsigned int id_type, unsigned int timeout_rc_type); 665 unsigned int id_type);
666 int (*preempt_ch_tsg)(struct gk20a *g, u32 id, 666 int (*preempt_ch_tsg)(struct gk20a *g, u32 id,
667 unsigned int id_type, unsigned int timeout_rc_type); 667 unsigned int id_type);
668 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); 668 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
669 int (*reset_enable_hw)(struct gk20a *g); 669 int (*reset_enable_hw)(struct gk20a *g);
670 int (*setup_userd)(struct channel_gk20a *c); 670 int (*setup_userd)(struct channel_gk20a *c);