diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2015-09-08 11:41:51 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-11 11:46:06 -0400 |
commit | 0398e0751f51d8ed04da1c32cc5979a0b9c47a43 (patch) | |
tree | d8f5777e44b7ef4c682e7572796e8da24141ffa8 /drivers/gpu/nvgpu/gk20a | |
parent | f6311b58b3c8072de6a4c09df010a517e6ef24f2 (diff) |
gpu: nvgpu: separate API to get failing engine data
In gk20a_fifo_handle_sched_error(), we currently have a sequence
to identify failing engine (stuck on context switch) and
corresponding failing channel with its type
Separate out this sequence in new API
gk20a_fifo_get_failing_engine_data() so that it can be
reused from else where too
Bug 200133289
Change-Id: I3cef395170cf8990c014c7505c798fd6f2e37921
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797070
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 |
2 files changed, 31 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b195cf88..68c0ddcb 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1357,16 +1357,13 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose) | |||
1357 | return 0; | 1357 | return 0; |
1358 | } | 1358 | } |
1359 | 1359 | ||
1360 | static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | 1360 | u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, |
1361 | int *__id, bool *__is_tsg) | ||
1361 | { | 1362 | { |
1362 | u32 sched_error; | 1363 | u32 engine_id = -1; |
1363 | u32 engine_id; | ||
1364 | int id = -1; | 1364 | int id = -1; |
1365 | bool non_chid = false; | 1365 | bool is_tsg = false; |
1366 | bool ret = false; | ||
1367 | u32 mailbox2; | 1366 | u32 mailbox2; |
1368 | /* read the scheduler error register */ | ||
1369 | sched_error = gk20a_readl(g, fifo_intr_sched_error_r()); | ||
1370 | 1367 | ||
1371 | for (engine_id = 0; engine_id < g->fifo.max_engines; engine_id++) { | 1368 | for (engine_id = 0; engine_id < g->fifo.max_engines; engine_id++) { |
1372 | u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id)); | 1369 | u32 status = gk20a_readl(g, fifo_engine_status_r(engine_id)); |
@@ -1388,13 +1385,14 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | |||
1388 | 1385 | ||
1389 | if (!failing_engine) | 1386 | if (!failing_engine) |
1390 | continue; | 1387 | continue; |
1388 | |||
1391 | if (ctx_status == | 1389 | if (ctx_status == |
1392 | fifo_engine_status_ctx_status_ctxsw_load_v()) { | 1390 | fifo_engine_status_ctx_status_ctxsw_load_v()) { |
1393 | id = fifo_engine_status_next_id_v(status); | 1391 | id = fifo_engine_status_next_id_v(status); |
1394 | non_chid = fifo_pbdma_status_id_type_v(status) | 1392 | is_tsg = fifo_pbdma_status_id_type_v(status) |
1395 | != fifo_pbdma_status_id_type_chid_v(); | 1393 | != fifo_pbdma_status_id_type_chid_v(); |
1396 | } else if (ctx_status == | 1394 | } else if (ctx_status == |
1397 | fifo_engine_status_ctx_status_ctxsw_switch_v()) { | 1395 | fifo_engine_status_ctx_status_ctxsw_switch_v()) { |
1398 | mailbox2 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(2)); | 1396 | mailbox2 = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(2)); |
1399 | if (mailbox2 & FECS_METHOD_WFI_RESTORE) | 1397 | if (mailbox2 & FECS_METHOD_WFI_RESTORE) |
1400 | id = fifo_engine_status_next_id_v(status); | 1398 | id = fifo_engine_status_next_id_v(status); |
@@ -1406,6 +1404,25 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | |||
1406 | break; | 1404 | break; |
1407 | } | 1405 | } |
1408 | 1406 | ||
1407 | *__id = id; | ||
1408 | *__is_tsg = is_tsg; | ||
1409 | |||
1410 | return engine_id; | ||
1411 | } | ||
1412 | |||
1413 | static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | ||
1414 | { | ||
1415 | u32 sched_error; | ||
1416 | u32 engine_id; | ||
1417 | int id = -1; | ||
1418 | bool is_tsg = false; | ||
1419 | bool ret = false; | ||
1420 | |||
1421 | /* read the scheduler error register */ | ||
1422 | sched_error = gk20a_readl(g, fifo_intr_sched_error_r()); | ||
1423 | |||
1424 | engine_id = gk20a_fifo_get_failing_engine_data(g, &id, &is_tsg); | ||
1425 | |||
1409 | /* could not find the engine - should never happen */ | 1426 | /* could not find the engine - should never happen */ |
1410 | if (unlikely(engine_id >= g->fifo.max_engines)) { | 1427 | if (unlikely(engine_id >= g->fifo.max_engines)) { |
1411 | gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, failed to find engine\n", | 1428 | gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, failed to find engine\n", |
@@ -1419,7 +1436,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | |||
1419 | struct fifo_gk20a *f = &g->fifo; | 1436 | struct fifo_gk20a *f = &g->fifo; |
1420 | struct channel_gk20a *ch = &f->channel[id]; | 1437 | struct channel_gk20a *ch = &f->channel[id]; |
1421 | 1438 | ||
1422 | if (non_chid) { | 1439 | if (is_tsg) { |
1423 | gk20a_fifo_recover(g, BIT(engine_id), id, true, | 1440 | gk20a_fifo_recover(g, BIT(engine_id), id, true, |
1424 | true, true); | 1441 | true, true); |
1425 | ret = true; | 1442 | ret = true; |
@@ -1453,7 +1470,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g) | |||
1453 | } | 1470 | } |
1454 | 1471 | ||
1455 | gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, engine=%u, %s=%d", | 1472 | gk20a_err(dev_from_gk20a(g), "fifo sched error : 0x%08x, engine=%u, %s=%d", |
1456 | sched_error, engine_id, non_chid ? "non-ch" : "ch", id); | 1473 | sched_error, engine_id, is_tsg ? "tsg" : "ch", id); |
1457 | 1474 | ||
1458 | err: | 1475 | err: |
1459 | return ret; | 1476 | return ret; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index bc9315d2..7385f9be 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -177,5 +177,7 @@ void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g, | |||
177 | int gk20a_fifo_wait_engine_idle(struct gk20a *g); | 177 | int gk20a_fifo_wait_engine_idle(struct gk20a *g); |
178 | u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g); | 178 | u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g); |
179 | u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g); | 179 | u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g); |
180 | u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, | ||
181 | int *__id, bool *__is_tsg); | ||
180 | 182 | ||
181 | #endif /*__GR_GK20A_H__*/ | 183 | #endif /*__GR_GK20A_H__*/ |