diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-23 07:18:33 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-16 06:10:37 -0400 |
commit | 0301cc01f6cbfb752290bc63a2ed4eb19129c7c1 (patch) | |
tree | fafe6562b8251c88f130f6368b9a41eb622669b9 /drivers/gpu/nvgpu/gk20a | |
parent | 4ff87c7d35f34e01e138cbedb143a37ff32a8926 (diff) |
gpu: nvgpu: add HAL to insert semaphore commands
Add below new HALs
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer
Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/
release sequence and set it to gops.fifo.add_sema_cmd()
Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size()
to return respective command buffer sizes
Jira NVGPUT-16
Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704490
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 54 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 6 |
4 files changed, 68 insertions, 36 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c index 68fbb738..7a664bf8 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c | |||
@@ -372,41 +372,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, | |||
372 | if (!acquire) | 372 | if (!acquire) |
373 | nvgpu_semaphore_prepare(s, c->hw_sema); | 373 | nvgpu_semaphore_prepare(s, c->hw_sema); |
374 | 374 | ||
375 | /* semaphore_a */ | 375 | g->ops.fifo.add_sema_cmd(g, s, va, cmd, off, acquire, wfi); |
376 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); | ||
377 | /* offset_upper */ | ||
378 | nvgpu_mem_wr32(g, cmd->mem, off++, (va >> 32) & 0xff); | ||
379 | /* semaphore_b */ | ||
380 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); | ||
381 | /* offset */ | ||
382 | nvgpu_mem_wr32(g, cmd->mem, off++, va & 0xffffffff); | ||
383 | |||
384 | if (acquire) { | ||
385 | /* semaphore_c */ | ||
386 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); | ||
387 | /* payload */ | ||
388 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
389 | nvgpu_semaphore_get_value(s)); | ||
390 | /* semaphore_d */ | ||
391 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); | ||
392 | /* operation: acq_geq, switch_en */ | ||
393 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); | ||
394 | } else { | ||
395 | /* semaphore_c */ | ||
396 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); | ||
397 | /* payload */ | ||
398 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
399 | nvgpu_semaphore_get_value(s)); | ||
400 | /* semaphore_d */ | ||
401 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); | ||
402 | /* operation: release, wfi */ | ||
403 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
404 | 0x2 | ((wfi ? 0x0 : 0x1) << 20)); | ||
405 | /* non_stall_int */ | ||
406 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008); | ||
407 | /* ignored */ | ||
408 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
409 | } | ||
410 | 376 | ||
411 | if (acquire) | 377 | if (acquire) |
412 | gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3d" | 378 | gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3d" |
@@ -495,7 +461,7 @@ static int __gk20a_channel_semaphore_incr( | |||
495 | return -ENOMEM; | 461 | return -ENOMEM; |
496 | } | 462 | } |
497 | 463 | ||
498 | incr_cmd_size = 10; | 464 | incr_cmd_size = c->g->ops.fifo.get_sema_incr_cmd_size(); |
499 | err = gk20a_channel_alloc_priv_cmdbuf(c, incr_cmd_size, incr_cmd); | 465 | err = gk20a_channel_alloc_priv_cmdbuf(c, incr_cmd_size, incr_cmd); |
500 | if (err) { | 466 | if (err) { |
501 | nvgpu_err(c->g, | 467 | nvgpu_err(c->g, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 0c3e8039..aada3065 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -4077,6 +4077,60 @@ const char *gk20a_fifo_interleave_level_name(u32 interleave_level) | |||
4077 | } | 4077 | } |
4078 | } | 4078 | } |
4079 | 4079 | ||
4080 | u32 gk20a_fifo_get_sema_wait_cmd_size(void) | ||
4081 | { | ||
4082 | return 8; | ||
4083 | } | ||
4084 | |||
4085 | u32 gk20a_fifo_get_sema_incr_cmd_size(void) | ||
4086 | { | ||
4087 | return 10; | ||
4088 | } | ||
4089 | |||
4090 | void gk20a_fifo_add_sema_cmd(struct gk20a *g, | ||
4091 | struct nvgpu_semaphore *s, u64 sema_va, | ||
4092 | struct priv_cmd_entry *cmd, | ||
4093 | u32 off, bool acquire, bool wfi) | ||
4094 | { | ||
4095 | nvgpu_log_fn(g, " "); | ||
4096 | |||
4097 | /* semaphore_a */ | ||
4098 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); | ||
4099 | /* offset_upper */ | ||
4100 | nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32) & 0xff); | ||
4101 | /* semaphore_b */ | ||
4102 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); | ||
4103 | /* offset */ | ||
4104 | nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffff); | ||
4105 | |||
4106 | if (acquire) { | ||
4107 | /* semaphore_c */ | ||
4108 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); | ||
4109 | /* payload */ | ||
4110 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
4111 | nvgpu_semaphore_get_value(s)); | ||
4112 | /* semaphore_d */ | ||
4113 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); | ||
4114 | /* operation: acq_geq, switch_en */ | ||
4115 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); | ||
4116 | } else { | ||
4117 | /* semaphore_c */ | ||
4118 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); | ||
4119 | /* payload */ | ||
4120 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
4121 | nvgpu_semaphore_get_value(s)); | ||
4122 | /* semaphore_d */ | ||
4123 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); | ||
4124 | /* operation: release, wfi */ | ||
4125 | nvgpu_mem_wr32(g, cmd->mem, off++, | ||
4126 | 0x2 | ((wfi ? 0x0 : 0x1) << 20)); | ||
4127 | /* non_stall_int */ | ||
4128 | nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008); | ||
4129 | /* ignored */ | ||
4130 | nvgpu_mem_wr32(g, cmd->mem, off++, 0); | ||
4131 | } | ||
4132 | } | ||
4133 | |||
4080 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 4134 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
4081 | void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g, | 4135 | void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g, |
4082 | struct priv_cmd_entry *cmd, u32 off, | 4136 | struct priv_cmd_entry *cmd, u32 off, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 20533f5d..7216302c 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -444,4 +444,10 @@ void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | |||
444 | void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault); | 444 | void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault); |
445 | void gk20a_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); | 445 | void gk20a_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); |
446 | void gk20a_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); | 446 | void gk20a_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); |
447 | u32 gk20a_fifo_get_sema_wait_cmd_size(void); | ||
448 | u32 gk20a_fifo_get_sema_incr_cmd_size(void); | ||
449 | void gk20a_fifo_add_sema_cmd(struct gk20a *g, | ||
450 | struct nvgpu_semaphore *s, u64 sema_va, | ||
451 | struct priv_cmd_entry *cmd, | ||
452 | u32 off, bool acquire, bool wfi); | ||
447 | #endif /*__GR_GK20A_H__*/ | 453 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 23e85ee9..17f662df 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -678,6 +678,12 @@ struct gpu_ops { | |||
678 | u32 count, u32 buffer_index); | 678 | u32 count, u32 buffer_index); |
679 | int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); | 679 | int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id); |
680 | void (*ring_channel_doorbell)(struct channel_gk20a *c); | 680 | void (*ring_channel_doorbell)(struct channel_gk20a *c); |
681 | u32 (*get_sema_wait_cmd_size)(void); | ||
682 | u32 (*get_sema_incr_cmd_size)(void); | ||
683 | void (*add_sema_cmd)(struct gk20a *g, | ||
684 | struct nvgpu_semaphore *s, u64 sema_va, | ||
685 | struct priv_cmd_entry *cmd, | ||
686 | u32 off, bool acquire, bool wfi); | ||
681 | } fifo; | 687 | } fifo; |
682 | struct pmu_v { | 688 | struct pmu_v { |
683 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 689 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |