gpu: nvgpu: gm20b expose gpcclk through CCF

Register gpcclk with Common Clock Framework to expose GPCPLL frequency
control

Bug 200233943

Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1236979
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 27 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index aefbc5d5..43583f2e 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -17,6 +17,7 @@
 #define CLK_GK20A_H
 
 #include <linux/mutex.h>
+#include <linux/clk-provider.h>
 
 #define GPUFREQ_TABLE_END     ~(u32)1
 enum {
@@ -79,6 +80,9 @@ struct namemap_cfg;
 struct clk_gk20a {
         struct gk20a *g;
         struct clk *tegra_clk;
+#if defined(CONFIG_COMMON_CLK)
+        struct clk_hw hw;
+#endif
         struct pll gpc_pll;
         struct pll gpc_pll_last;
         struct mutex clk_mutex;
@@ -89,6 +93,10 @@ struct clk_gk20a {
         bool debugfs_set;
 };
 
+#if defined(CONFIG_COMMON_CLK)
+#define to_clk_gk20a(_hw) container_of(_hw, struct clk_gk20a, hw)
+#endif
+
 struct gpu_ops;
 #ifdef CONFIG_TEGRA_CLK_FRAMEWORK
 void gk20a_init_clk_ops(struct gpu_ops *gops);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
index 55ebcc8f..d60fce33 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
@@ -636,9 +636,12 @@ static ssize_t fmax_at_vmin_safe_read(struct device *dev,
 {
         struct gk20a *g = get_gk20a(dev);
         unsigned long gpu_fmax_at_vmin_hz = 0;
+        struct clk *clk = g->clk.tegra_clk;
 
-        gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t(
-                clk_get_parent(g->clk.tegra_clk));
+#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
+        clk = clk_get_parent(clk);
+#endif
+        gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t(clk);
 
         return snprintf(buf, PAGE_SIZE, "%d\n", (int)(gpu_fmax_at_vmin_hz));
 }
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
index 94b8d157..f13a11ea 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
@@ -179,6 +179,8 @@ struct gk20a_platform {
         int (*clk_set_rate)(struct device *dev,
                                 unsigned long rate);
 
+        /* Called to register GPCPLL with common clk framework */
+        int (*clk_register)(struct gk20a *g);
 
         /* Postscale callback is called after frequency change */
         void (*postscale)(struct device *dev,
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
index 40e7cead..35d524f1 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
@@ -40,6 +40,7 @@
 #include "hal_gk20a.h"
 #include "platform_gk20a.h"
 #include "gk20a_scale.h"
+#include "gm20b/clk_gm20b.h"
 
 #define TEGRA_GK20A_BW_PER_FREQ 32
 #define TEGRA_GM20B_BW_PER_FREQ 64
@@ -787,6 +788,7 @@ static int gk20a_tegra_probe(struct device *dev)
         const __be32 *host1x_ptr;
         struct platform_device *host1x_pdev = NULL;
         bool joint_xpu_rail = false;
+        int ret;
 
         host1x_ptr = of_get_property(np, "nvidia,host1x", NULL);
         if (host1x_ptr) {
@@ -834,6 +836,12 @@ static int gk20a_tegra_probe(struct device *dev)
 
         gk20a_tegra_get_clocks(dev);
 
+        if (platform->clk_register) {
+                ret = platform->clk_register(platform->g);
+                if (ret)
+                        return ret;
+        }
+
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
         pmc = ioremap(TEGRA_PMC_BASE, 4096);
 #endif
@@ -1019,6 +1027,10 @@ struct gk20a_platform gm20b_tegra_platform = {
         .get_clk_freqs = gk20a_clk_get_freqs,
 #endif
 
+#ifdef CONFIG_COMMON_CLK
+        .clk_register = gm20b_register_gpcclk,
+#endif
+
         /* frequency scaling configuration */
         .prescale = gk20a_tegra_prescale,
         .postscale = gk20a_tegra_postscale,