gpu: nvgpu: Move SM_MASK_TYPE setting to TSG level

Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.

In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.

Bug 200412641

Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
index 67ccb9f5..1e3be553 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
@@ -78,6 +78,10 @@ struct tsg_gk20a {
         bool in_use;
 
         struct nvgpu_tsg_sm_error_state *sm_error_states;
+
+#define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE               (0x0U)
+#define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL              (0x1U << 0)
+        u32 sm_exception_mask_type;
 };
 
 int gk20a_enable_tsg(struct tsg_gk20a *tsg);