gpu: nvgpu: Reduce structure padding waste

The gk20a_init_fifo_setup_sw_common() function allocates memory of
schannel_gk20a and tsg_gk20a tructures for all 512 channels:
    Size   Caller                    Module  Pages     Type
    749568 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=182 vmalloc
    602112 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=146 vmalloc

This change just simply reorgnizes the member defines in those two
structures to reduce padding waste. After this change:
    Size   Caller                    Module  Pages     Type
    733184 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=178 vmalloc
    585728 __nvgpu_vzalloc+0x28/0x78 [nvgpu] pages=142 vmalloc

In summary, it saves 8 pages in 32KB memory.

Bug 2327574
Bug 2284925

Change-Id: I06693e0fef516a145b48dd3a05d756c0feaf3ba5
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803358
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 9 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
index 2f76477f..552c3bb3 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
@@ -42,34 +42,33 @@ struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch);
 struct tsg_gk20a {
         struct gk20a *g;
 
-        bool in_use;
-        int tsgid;
+        struct vm_gk20a *vm;
+        struct nvgpu_mem *eng_method_buffers;
+
 
+        struct nvgpu_gr_ctx gr_ctx;
         struct nvgpu_ref refcount;
 
         struct nvgpu_list_node ch_list;
-        int num_active_channels;
+        struct nvgpu_list_node event_id_list;
         struct nvgpu_rwsem ch_list_lock;
+        struct nvgpu_mutex event_id_list_lock;
+        int num_active_channels;
 
         unsigned int timeslice_us;
         unsigned int timeslice_timeout;
         unsigned int timeslice_scale;
 
-        struct vm_gk20a *vm;
-
         u32 interleave_level;
-
-        struct nvgpu_list_node event_id_list;
-        struct nvgpu_mutex event_id_list_lock;
+        int tsgid;
 
         u32 runlist_id;
         pid_t tgid;
-        struct nvgpu_mem *eng_method_buffers;
         u32  num_active_tpcs;
         u8   tpc_pg_enabled;
         bool tpc_num_initialized;
+        bool in_use;
 
-        struct nvgpu_gr_ctx gr_ctx;
 };
 
 int gk20a_enable_tsg(struct tsg_gk20a *tsg);