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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-12-15 12:04:15 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-17 15:29:09 -0500
commit2f6698b863c9cc1db6455637b7c72e812b470b93 (patch)
treed0c8abf32d6994b9f54bf5eddafd8316e038c829 /drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
parent6a73114788ffafe4c53771c707ecbd9c9ea0a117 (diff)
gpu: nvgpu: Make graphics context property of TSG
Move graphics context ownership to TSG instead of channel. Combine channel_ctx_gk20a and gr_ctx_desc to one structure, because the split between them was arbitrary. Move context header to be property of channel. Bug 1842197 Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639532 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/tsg_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/tsg_gk20a.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
index 08fe0365..2168cb4f 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
@@ -26,6 +26,8 @@
26#include <nvgpu/kref.h> 26#include <nvgpu/kref.h>
27#include <nvgpu/rwsem.h> 27#include <nvgpu/rwsem.h>
28 28
29#include "gr_gk20a.h"
30
29#ifdef CONFIG_TEGRA_19x_GPU 31#ifdef CONFIG_TEGRA_19x_GPU
30#include "tsg_t19x.h" 32#include "tsg_t19x.h"
31#endif 33#endif
@@ -56,8 +58,6 @@ struct tsg_gk20a {
56 unsigned int timeslice_timeout; 58 unsigned int timeslice_timeout;
57 unsigned int timeslice_scale; 59 unsigned int timeslice_scale;
58 60
59 struct gr_ctx_desc *tsg_gr_ctx;
60
61 struct vm_gk20a *vm; 61 struct vm_gk20a *vm;
62 62
63 u32 interleave_level; 63 u32 interleave_level;
@@ -71,6 +71,8 @@ struct tsg_gk20a {
71#ifdef CONFIG_TEGRA_19x_GPU 71#ifdef CONFIG_TEGRA_19x_GPU
72 struct tsg_t19x t19x; 72 struct tsg_t19x t19x;
73#endif 73#endif
74
75 struct nvgpu_gr_ctx gr_ctx;
74}; 76};
75 77
76int gk20a_enable_tsg(struct tsg_gk20a *tsg); 78int gk20a_enable_tsg(struct tsg_gk20a *tsg);