gpu: nvgpu: IOCTL to set TSG timeslice

Add new IOCTL NVGPU_IOCTL_TSG_SET_PRIORITY to allow
setting timeslice for entire TSG

Return error from channel specific IOCTL_CHANNEL_SET_PRIORITY
if the channel is part of TSG

Separate out API gk20a_channel_get_timescale_from_timeslice()
to get timeslice_timeout and scale from timeslice period

Use this API to get timeslice_timeout and scale for TSG and
store it in tsg_gk20a structure

Then trigger runlist update so that new timeslice values
will be re-written to runlist for TSG

Bug 200146615

Change-Id: I555467d034f81b372b31372f0835d72b1c159508
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/824206
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 36 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 37a326d2..5cd43329 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -126,6 +126,34 @@ int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid)
         return 0;
 }
 
+static int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
+                                u32 priority)
+{
+        int timeslice_period;
+
+        switch (priority) {
+        case NVGPU_PRIORITY_LOW:
+                timeslice_period = g->timeslice_low_priority_us;
+                break;
+        case NVGPU_PRIORITY_MEDIUM:
+                timeslice_period = g->timeslice_medium_priority_us;
+                break;
+        case NVGPU_PRIORITY_HIGH:
+                timeslice_period = g->timeslice_high_priority_us;
+                break;
+        default:
+                pr_err("Unsupported priority");
+                return -EINVAL;
+        }
+
+        gk20a_channel_get_timescale_from_timeslice(g, timeslice_period,
+                        &tsg->timeslice_timeout, &tsg->timeslice_scale);
+
+        g->ops.fifo.update_runlist(g, 0, ~0, true, true);
+
+        return 0;
+}
+
 static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg)
 {
         mutex_lock(&f->tsg_inuse_mutex);
@@ -320,6 +348,13 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
                 break;
                 }
 
+        case NVGPU_IOCTL_TSG_SET_PRIORITY:
+                {
+                err = gk20a_tsg_set_priority(g, tsg,
+                        ((struct nvgpu_set_priority_args *)buf)->priority);
+                break;
+                }
+
         default:
                 gk20a_err(dev_from_gk20a(g),
                            "unrecognized tsg gpu ioctl cmd: 0x%x",