gpu: nvgpu: define runlist level in common code

All the runlist levels NVGPU_RUNLIST_INTERLEAVE_LEVEL_* are declared in linux
specific uapi header and used in common code
But since common code should be linux-independent, move these uses out of
common code

Define new runlist levels NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* in common code
and use them wherever required

Add new API nvgpu_get_common_runlist_level() to get common runlist level of
the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* from linux specific runlist
level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*

Jira NVGPU-259

Change-Id: Ic19239f0f8275683d5d1b981df530acd90e6dfbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594327
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index badc7ef9..640174a6 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -229,9 +229,9 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
         gk20a_dbg(gpu_dbg_sched, "tsgid=%u interleave=%u", tsg->tsgid, level);
 
         switch (level) {
-        case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
-        case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
-        case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
+        case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
+        case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
+        case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
                 ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid,
                                                         true, 0, level);
                 if (!ret)
@@ -304,7 +304,7 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g)
 
         tsg->tsg_gr_ctx = NULL;
         tsg->vm = NULL;
-        tsg->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW;
+        tsg->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
         tsg->timeslice_us = 0;
         tsg->timeslice_timeout = 0;
         tsg->timeslice_scale = 0;