gpu: nvgpu: Move ELCG programming to therm

Move ELCG parameter programming to a new function in therm,
elcg_init_idle_filter. Implement gk20a variant and use it for gk20a
and gm20b.

JIRA DNVGPU-74

Change-Id: I8ef400f3a6195311fb9e7da8db6c34993d62f461
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1220433
(cherry picked from commit f6654ae4d83d31cd40b317bf55922964bbfa575d)
Reviewed-on: http://git-master/r/1239421
GVS: Gerrit_Virtual_Submit

1 files changed, 44 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
index da8e2894..e983a814 100644
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
@@ -110,7 +110,51 @@ int gk20a_init_therm_support(struct gk20a *g)
         return err;
 }
 
+int gk20a_elcg_init_idle_filters(struct gk20a *g)
+{
+        u32 gate_ctrl, idle_filter;
+        u32 engine_id;
+        u32 active_engine_id = 0;
+        struct fifo_gk20a *f = &g->fifo;
+        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+
+        gk20a_dbg_fn("");
+
+        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
+                active_engine_id = f->active_engines_list[engine_id];
+                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
+
+                if (platform->is_fmodel) {
+                        gate_ctrl = set_field(gate_ctrl,
+                                therm_gate_ctrl_eng_delay_after_m(),
+                                therm_gate_ctrl_eng_delay_after_f(4));
+                }
+
+                /* 2 * (1 << 9) = 1024 clks */
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_idle_filt_exp_m(),
+                        therm_gate_ctrl_eng_idle_filt_exp_f(9));
+                gate_ctrl = set_field(gate_ctrl,
+                        therm_gate_ctrl_eng_idle_filt_mant_m(),
+                        therm_gate_ctrl_eng_idle_filt_mant_f(2));
+                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
+        }
+
+        /* default fecs_idle_filter to 0 */
+        idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
+        idle_filter &= ~therm_fecs_idle_filter_value_m();
+        gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
+        /* default hubmmu_idle_filter to 0 */
+        idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
+        idle_filter &= ~therm_hubmmu_idle_filter_value_m();
+        gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
+
+        gk20a_dbg_fn("done");
+        return 0;
+}
+
 void gk20a_init_therm_ops(struct gpu_ops *gops)
 {
         gops->therm.init_therm_setup_hw = gk20a_init_therm_setup_hw;
+        gops->therm.elcg_init_idle_filters = gk20a_elcg_init_idle_filters;
 }