gpu: nvgpu: Move therm HAL to common

Move implementation of therm HAL to common/therm. ELCG and BLCG
code was embedded in gr HAL, so moved that code to therm.

Bump gk20a code to gm20b.

JIRA NVGPU-955

Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 111 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
deleted file mode 100644
index b4a81aed..00000000
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * GK20A Therm
- *
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/enabled.h>
-#include <nvgpu/io.h>
-#include <nvgpu/utils.h>
-
-#include "gk20a.h"
-
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_therm_gk20a.h>
-
-static int gk20a_init_therm_reset_enable_hw(struct gk20a *g)
-{
-        return 0;
-}
-
-static int gk20a_init_therm_setup_sw(struct gk20a *g)
-{
-        return 0;
-}
-
-int gk20a_init_therm_support(struct gk20a *g)
-{
-        u32 err;
-
-        nvgpu_log_fn(g, " ");
-
-        err = gk20a_init_therm_reset_enable_hw(g);
-        if (err)
-                return err;
-
-        err = gk20a_init_therm_setup_sw(g);
-        if (err)
-                return err;
-
-        if (g->ops.therm.init_therm_setup_hw)
-                err = g->ops.therm.init_therm_setup_hw(g);
-        if (err)
-                return err;
-
-#ifdef CONFIG_DEBUG_FS
-        if (g->ops.therm.therm_debugfs_init)
-            g->ops.therm.therm_debugfs_init(g);
-#endif
-
-        return err;
-}
-
-int gk20a_elcg_init_idle_filters(struct gk20a *g)
-{
-        u32 gate_ctrl, idle_filter;
-        u32 engine_id;
-        u32 active_engine_id = 0;
-        struct fifo_gk20a *f = &g->fifo;
-
-        nvgpu_log_fn(g, " ");
-
-        for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
-                active_engine_id = f->active_engines_list[engine_id];
-                gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
-
-                if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                        gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_delay_after_m(),
-                                therm_gate_ctrl_eng_delay_after_f(4));
-                }
-
-                /* 2 * (1 << 9) = 1024 clks */
-                gate_ctrl = set_field(gate_ctrl,
-                        therm_gate_ctrl_eng_idle_filt_exp_m(),
-                        therm_gate_ctrl_eng_idle_filt_exp_f(9));
-                gate_ctrl = set_field(gate_ctrl,
-                        therm_gate_ctrl_eng_idle_filt_mant_m(),
-                        therm_gate_ctrl_eng_idle_filt_mant_f(2));
-                gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
-        }
-
-        /* default fecs_idle_filter to 0 */
-        idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
-        idle_filter &= ~therm_fecs_idle_filter_value_m();
-        gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
-        /* default hubmmu_idle_filter to 0 */
-        idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
-        idle_filter &= ~therm_hubmmu_idle_filter_value_m();
-        gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
-
-        nvgpu_log_fn(g, "done");
-        return 0;
-}