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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-10-27 03:16:51 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:52 -0400
commit4739499f07b29282ee1031d08adaa76c238da2a6 (patch)
tree10caa152eea6250e46cad6172553069b4bb3dcb9 /drivers/gpu/nvgpu/gk20a/therm_gk20a.c
parentb5bb4f53dbdde8473e1160d4522c5d9da55f115f (diff)
gpu: nvgpu: Sync gk20a and gm20b headers
Synchronize gk20a and gm20b headers. All registers which were added to gk20a are now added to gm20b, and some registers that are unused are removed. Bug 1567274 Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590313 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/therm_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/therm_gk20a.c73
1 files changed, 0 insertions, 73 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
index da911979..b02113ad 100644
--- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c
@@ -20,7 +20,6 @@
20 */ 20 */
21 21
22#include "gk20a.h" 22#include "gk20a.h"
23#include "hw_chiplet_pwr_gk20a.h"
24#include "hw_gr_gk20a.h" 23#include "hw_gr_gk20a.h"
25#include "hw_therm_gk20a.h" 24#include "hw_therm_gk20a.h"
26 25
@@ -45,78 +44,6 @@ static int gk20a_init_therm_setup_hw(struct gk20a *g)
45 gk20a_writel(g, therm_evt_ext_therm_2_r(), 44 gk20a_writel(g, therm_evt_ext_therm_2_r(),
46 NV_THERM_EVT_EXT_THERM_2_INIT); 45 NV_THERM_EVT_EXT_THERM_2_INIT);
47 46
48/*
49 u32 data;
50
51 data = gk20a_readl(g, gr_gpcs_tpcs_l1c_cfg_r());
52 data = set_field(data, gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_m(),
53 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_enable_f());
54 gk20a_writel(g, gr_gpcs_tpcs_l1c_cfg_r(), data);
55
56 data = gk20a_readl(g, gr_gpcs_tpcs_l1c_pm_r());
57 data = set_field(data, gr_gpcs_tpcs_l1c_pm_enable_m(),
58 gr_gpcs_tpcs_l1c_pm_enable_enable_f());
59 gk20a_writel(g, gr_gpcs_tpcs_l1c_pm_r(), data);
60
61 data = gk20a_readl(g, gr_gpcs_tpcs_sm_pm_ctrl_r());
62 data = set_field(data, gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(),
63 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f());
64 data = set_field(data, gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(),
65 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f());
66 gk20a_writel(g, gr_gpcs_tpcs_sm_pm_ctrl_r(), data);
67
68 data = gk20a_readl(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r());
69 data = set_field(data, gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_m(),
70 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_enable_f());
71 gk20a_writel(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r(), data);
72
73 data = gk20a_readl(g, gr_gpcs_tpcs_sm_debug_sfe_control_r());
74 data = set_field(data, gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_m(),
75 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_enable_f());
76 gk20a_writel(g, gr_gpcs_tpcs_sm_debug_sfe_control_r(), data);
77
78 gk20a_writel(g, therm_peakpower_config6_r(0),
79 therm_peakpower_config6_trigger_cfg_1h_intr_f() |
80 therm_peakpower_config6_trigger_cfg_1l_intr_f());
81
82 gk20a_writel(g, chiplet_pwr_gpcs_config_1_r(),
83 chiplet_pwr_gpcs_config_1_ba_enable_yes_f());
84 gk20a_writel(g, chiplet_pwr_fbps_config_1_r(),
85 chiplet_pwr_fbps_config_1_ba_enable_yes_f());
86
87 data = gk20a_readl(g, therm_config1_r());
88 data = set_field(data, therm_config1_ba_enable_m(),
89 therm_config1_ba_enable_yes_f());
90 gk20a_writel(g, therm_config1_r(), data);
91
92 gk20a_writel(g, gr_gpcs_tpcs_sm_power_throttle_r(), 0x441a);
93
94 gk20a_writel(g, therm_weight_1_r(), 0xd3);
95 gk20a_writel(g, chiplet_pwr_gpcs_weight_6_r(), 0x7d);
96 gk20a_writel(g, chiplet_pwr_gpcs_weight_7_r(), 0xff);
97 gk20a_writel(g, chiplet_pwr_fbps_weight_0_r(), 0x13000000);
98 gk20a_writel(g, chiplet_pwr_fbps_weight_1_r(), 0x19);
99
100 gk20a_writel(g, therm_peakpower_config8_r(0), 0x8);
101 gk20a_writel(g, therm_peakpower_config9_r(0), 0x0);
102
103 gk20a_writel(g, therm_evt_ba_w0_t1h_r(), 0x100);
104
105 gk20a_writel(g, therm_use_a_r(), therm_use_a_ba_w0_t1h_yes_f());
106
107 gk20a_writel(g, therm_peakpower_config1_r(0),
108 therm_peakpower_config1_window_period_2m_f() |
109 therm_peakpower_config1_ba_sum_shift_20_f() |
110 therm_peakpower_config1_window_en_enabled_f());
111
112 gk20a_writel(g, therm_peakpower_config2_r(0),
113 therm_peakpower_config2_ba_threshold_1h_val_f(1) |
114 therm_peakpower_config2_ba_threshold_1h_en_enabled_f());
115
116 gk20a_writel(g, therm_peakpower_config4_r(0),
117 therm_peakpower_config4_ba_threshold_1l_val_f(1) |
118 therm_peakpower_config4_ba_threshold_1l_en_enabled_f());
119*/
120 return 0; 47 return 0;
121} 48}
122 49