diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-17 13:15:32 -0400 |
---|---|---|
committer | Bharat Nihalani <bnihalani@nvidia.com> | 2017-03-21 00:49:28 -0400 |
commit | 526cb049984fdc9b37af4d39c41bfe00db3b6898 (patch) | |
tree | ff85cda4248b6db3f605b3717427ee09686c3827 /drivers/gpu/nvgpu/gk20a/sim_gk20a.c | |
parent | 66cd2f7a187bf3d4ae7f432d6c79ed5abf544e02 (diff) |
gpu: nvgpu: Move sim support to its own file
Simulator support is intermixed with the rest of code in gk20a.c.
Move that code away from gk20a.c to an own file.
Change-Id: Idd3c8795cec5eadc6e49811b5b8ff0592c49a7d2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323230
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/sim_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.c | 345 |
1 files changed, 345 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c new file mode 100644 index 00000000..76d29ee5 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c | |||
@@ -0,0 +1,345 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/io.h> | ||
18 | #include <linux/highmem.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | |||
21 | #include "gk20a.h" | ||
22 | |||
23 | #include <nvgpu/hw/gk20a/hw_sim_gk20a.h> | ||
24 | |||
25 | static inline void sim_writel(struct gk20a *g, u32 r, u32 v) | ||
26 | { | ||
27 | writel(v, g->sim.regs + r); | ||
28 | } | ||
29 | |||
30 | static inline u32 sim_readl(struct gk20a *g, u32 r) | ||
31 | { | ||
32 | return readl(g->sim.regs + r); | ||
33 | } | ||
34 | |||
35 | static void kunmap_and_free_iopage(void **kvaddr, struct page **page) | ||
36 | { | ||
37 | if (*kvaddr) { | ||
38 | kunmap(*kvaddr); | ||
39 | *kvaddr = NULL; | ||
40 | } | ||
41 | if (*page) { | ||
42 | __free_page(*page); | ||
43 | *page = NULL; | ||
44 | } | ||
45 | } | ||
46 | |||
47 | static void gk20a_free_sim_support(struct gk20a *g) | ||
48 | { | ||
49 | /* free sim mappings, bfrs */ | ||
50 | kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, | ||
51 | &g->sim.send_bfr.page); | ||
52 | |||
53 | kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, | ||
54 | &g->sim.recv_bfr.page); | ||
55 | |||
56 | kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, | ||
57 | &g->sim.msg_bfr.page); | ||
58 | } | ||
59 | |||
60 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | ||
61 | { | ||
62 | struct gk20a *g = s->g; | ||
63 | if (g->sim.regs) | ||
64 | sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); | ||
65 | gk20a_free_sim_support(g); | ||
66 | } | ||
67 | |||
68 | static int alloc_and_kmap_iopage(struct device *d, | ||
69 | void **kvaddr, | ||
70 | u64 *phys, | ||
71 | struct page **page) | ||
72 | { | ||
73 | int err = 0; | ||
74 | *page = alloc_page(GFP_KERNEL); | ||
75 | |||
76 | if (!*page) { | ||
77 | err = -ENOMEM; | ||
78 | dev_err(d, "couldn't allocate io page\n"); | ||
79 | goto fail; | ||
80 | } | ||
81 | |||
82 | *kvaddr = kmap(*page); | ||
83 | if (!*kvaddr) { | ||
84 | err = -ENOMEM; | ||
85 | dev_err(d, "couldn't kmap io page\n"); | ||
86 | goto fail; | ||
87 | } | ||
88 | *phys = page_to_phys(*page); | ||
89 | return 0; | ||
90 | |||
91 | fail: | ||
92 | kunmap_and_free_iopage(kvaddr, page); | ||
93 | return err; | ||
94 | |||
95 | } | ||
96 | |||
97 | int gk20a_init_sim_support(struct platform_device *pdev) | ||
98 | { | ||
99 | int err = 0; | ||
100 | struct device *dev = &pdev->dev; | ||
101 | struct gk20a *g = get_gk20a(dev); | ||
102 | u64 phys; | ||
103 | |||
104 | g->sim.g = g; | ||
105 | g->sim.regs = gk20a_ioremap_resource(pdev, GK20A_SIM_IORESOURCE_MEM, | ||
106 | &g->sim.reg_mem); | ||
107 | if (IS_ERR(g->sim.regs)) { | ||
108 | dev_err(dev, "failed to remap gk20a sim regs\n"); | ||
109 | err = PTR_ERR(g->sim.regs); | ||
110 | goto fail; | ||
111 | } | ||
112 | |||
113 | /* allocate sim event/msg buffers */ | ||
114 | err = alloc_and_kmap_iopage(dev, &g->sim.send_bfr.kvaddr, | ||
115 | &g->sim.send_bfr.phys, | ||
116 | &g->sim.send_bfr.page); | ||
117 | |||
118 | err = err || alloc_and_kmap_iopage(dev, &g->sim.recv_bfr.kvaddr, | ||
119 | &g->sim.recv_bfr.phys, | ||
120 | &g->sim.recv_bfr.page); | ||
121 | |||
122 | err = err || alloc_and_kmap_iopage(dev, &g->sim.msg_bfr.kvaddr, | ||
123 | &g->sim.msg_bfr.phys, | ||
124 | &g->sim.msg_bfr.page); | ||
125 | |||
126 | if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && | ||
127 | g->sim.msg_bfr.kvaddr)) { | ||
128 | dev_err(dev, "couldn't allocate all sim buffers\n"); | ||
129 | goto fail; | ||
130 | } | ||
131 | |||
132 | /*mark send ring invalid*/ | ||
133 | sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); | ||
134 | |||
135 | /*read get pointer and make equal to put*/ | ||
136 | g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); | ||
137 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
138 | |||
139 | /*write send ring address and make it valid*/ | ||
140 | phys = g->sim.send_bfr.phys; | ||
141 | sim_writel(g, sim_send_ring_hi_r(), | ||
142 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | ||
143 | sim_writel(g, sim_send_ring_r(), | ||
144 | sim_send_ring_status_valid_f() | | ||
145 | sim_send_ring_target_phys_pci_coherent_f() | | ||
146 | sim_send_ring_size_4kb_f() | | ||
147 | sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
148 | |||
149 | /*repeat for recv ring (but swap put,get as roles are opposite) */ | ||
150 | sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); | ||
151 | |||
152 | /*read put pointer and make equal to get*/ | ||
153 | g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); | ||
154 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
155 | |||
156 | /*write send ring address and make it valid*/ | ||
157 | phys = g->sim.recv_bfr.phys; | ||
158 | sim_writel(g, sim_recv_ring_hi_r(), | ||
159 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | ||
160 | sim_writel(g, sim_recv_ring_r(), | ||
161 | sim_recv_ring_status_valid_f() | | ||
162 | sim_recv_ring_target_phys_pci_coherent_f() | | ||
163 | sim_recv_ring_size_4kb_f() | | ||
164 | sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); | ||
165 | |||
166 | g->sim.remove_support = gk20a_remove_sim_support; | ||
167 | return 0; | ||
168 | |||
169 | fail: | ||
170 | gk20a_free_sim_support(g); | ||
171 | return err; | ||
172 | } | ||
173 | |||
174 | static inline u32 sim_msg_header_size(void) | ||
175 | { | ||
176 | return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ | ||
177 | } | ||
178 | |||
179 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | ||
180 | { | ||
181 | return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); | ||
182 | } | ||
183 | |||
184 | static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) | ||
185 | { | ||
186 | return sim_msg_bfr(g, byte_offset); /*starts at 0*/ | ||
187 | } | ||
188 | |||
189 | static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) | ||
190 | { | ||
191 | /*starts after msg header/cmn*/ | ||
192 | return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); | ||
193 | } | ||
194 | |||
195 | static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) | ||
196 | { | ||
197 | /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ | ||
198 | *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); | ||
199 | *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); | ||
200 | *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); | ||
201 | *sim_msg_hdr(g, sim_msg_function_r()) = func; | ||
202 | *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); | ||
203 | } | ||
204 | |||
205 | static inline u32 sim_escape_read_hdr_size(void) | ||
206 | { | ||
207 | return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ | ||
208 | } | ||
209 | |||
210 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
211 | { | ||
212 | return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); | ||
213 | } | ||
214 | |||
215 | static int rpc_send_message(struct gk20a *g) | ||
216 | { | ||
217 | /* calculations done in units of u32s */ | ||
218 | u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; | ||
219 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | ||
220 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | ||
221 | |||
222 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | ||
223 | sim_dma_target_phys_pci_coherent_f() | | ||
224 | sim_dma_status_valid_f() | | ||
225 | sim_dma_size_4kb_f() | | ||
226 | sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); | ||
227 | |||
228 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | ||
229 | u64_hi32(g->sim.msg_bfr.phys); | ||
230 | |||
231 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; | ||
232 | |||
233 | g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % | ||
234 | PAGE_SIZE; | ||
235 | |||
236 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
237 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
238 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
239 | |||
240 | /* Update the put pointer. This will trap into the host. */ | ||
241 | sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); | ||
242 | |||
243 | return 0; | ||
244 | } | ||
245 | |||
246 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | ||
247 | { | ||
248 | return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); | ||
249 | } | ||
250 | |||
251 | static int rpc_recv_poll(struct gk20a *g) | ||
252 | { | ||
253 | u64 recv_phys_addr; | ||
254 | |||
255 | /* XXX This read is not required (?) */ | ||
256 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ | ||
257 | |||
258 | /* Poll the recv ring get pointer in an infinite loop*/ | ||
259 | do { | ||
260 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
261 | } while (g->sim.recv_ring_put == g->sim.recv_ring_get); | ||
262 | |||
263 | /* process all replies */ | ||
264 | while (g->sim.recv_ring_put != g->sim.recv_ring_get) { | ||
265 | /* these are in u32 offsets*/ | ||
266 | u32 dma_lo_offset = | ||
267 | sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; | ||
268 | u32 dma_hi_offset = dma_lo_offset + 1; | ||
269 | u32 recv_phys_addr_lo = sim_dma_addr_lo_v( | ||
270 | *sim_recv_ring_bfr(g, dma_lo_offset*4)); | ||
271 | u32 recv_phys_addr_hi = sim_dma_hi_addr_v( | ||
272 | *sim_recv_ring_bfr(g, dma_hi_offset*4)); | ||
273 | |||
274 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | | ||
275 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | ||
276 | |||
277 | if (recv_phys_addr != g->sim.msg_bfr.phys) { | ||
278 | dev_err(dev_from_gk20a(g), "%s Error in RPC reply\n", | ||
279 | __func__); | ||
280 | return -1; | ||
281 | } | ||
282 | |||
283 | /* Update GET pointer */ | ||
284 | g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % | ||
285 | PAGE_SIZE; | ||
286 | |||
287 | __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); | ||
288 | __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); | ||
289 | __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); | ||
290 | |||
291 | sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); | ||
292 | |||
293 | g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); | ||
294 | } | ||
295 | |||
296 | return 0; | ||
297 | } | ||
298 | |||
299 | static int issue_rpc_and_wait(struct gk20a *g) | ||
300 | { | ||
301 | int err; | ||
302 | |||
303 | err = rpc_send_message(g); | ||
304 | if (err) { | ||
305 | dev_err(dev_from_gk20a(g), "%s failed rpc_send_message\n", | ||
306 | __func__); | ||
307 | return err; | ||
308 | } | ||
309 | |||
310 | err = rpc_recv_poll(g); | ||
311 | if (err) { | ||
312 | dev_err(dev_from_gk20a(g), "%s failed rpc_recv_poll\n", | ||
313 | __func__); | ||
314 | return err; | ||
315 | } | ||
316 | |||
317 | /* Now check if RPC really succeeded */ | ||
318 | if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { | ||
319 | dev_err(dev_from_gk20a(g), "%s received failed status!\n", | ||
320 | __func__); | ||
321 | return -(*sim_msg_hdr(g, sim_msg_result_r())); | ||
322 | } | ||
323 | return 0; | ||
324 | } | ||
325 | |||
326 | int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) | ||
327 | { | ||
328 | int err; | ||
329 | size_t pathlen = strlen(path); | ||
330 | u32 data_offset; | ||
331 | |||
332 | sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), | ||
333 | sim_escape_read_hdr_size()); | ||
334 | *sim_msg_param(g, 0) = index; | ||
335 | *sim_msg_param(g, 4) = sizeof(u32); | ||
336 | data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); | ||
337 | *sim_msg_param(g, 8) = data_offset; | ||
338 | strcpy((char *)sim_msg_param(g, 0xc), path); | ||
339 | |||
340 | err = issue_rpc_and_wait(g); | ||
341 | |||
342 | if (!err) | ||
343 | memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); | ||
344 | return err; | ||
345 | } | ||