diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2017-11-13 03:21:48 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-23 06:03:36 -0500 |
commit | 536ec21b565ab1368b53a26d6ec7ed05857f0775 (patch) | |
tree | 5f385385ae730dd2d98463502d249150262f8b9b /drivers/gpu/nvgpu/gk20a/regops_gk20a.h | |
parent | ba2e59dc41f593bb011e0ec58c969337a35f4cf1 (diff) |
gpu: nvgpu: remove dependency on linux header for regops_gk20a*
This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.
1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.
JIRA NVGPU-417
Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/regops_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.h | 50 |
1 files changed, 48 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h index 4db79397..236fb52c 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h | |||
@@ -24,17 +24,63 @@ | |||
24 | #ifndef REGOPS_GK20A_H | 24 | #ifndef REGOPS_GK20A_H |
25 | #define REGOPS_GK20A_H | 25 | #define REGOPS_GK20A_H |
26 | 26 | ||
27 | /* | ||
28 | * Register operations | ||
29 | * All operations are targeted towards first channel | ||
30 | * attached to debug session | ||
31 | */ | ||
32 | /* valid op values */ | ||
33 | #define NVGPU_DBG_REG_OP_READ_32 (0x00000000) | ||
34 | #define NVGPU_DBG_REG_OP_WRITE_32 (0x00000001) | ||
35 | #define NVGPU_DBG_REG_OP_READ_64 (0x00000002) | ||
36 | #define NVGPU_DBG_REG_OP_WRITE_64 (0x00000003) | ||
37 | /* note: 8b ops are unsupported */ | ||
38 | #define NVGPU_DBG_REG_OP_READ_08 (0x00000004) | ||
39 | #define NVGPU_DBG_REG_OP_WRITE_08 (0x00000005) | ||
40 | |||
41 | /* valid type values */ | ||
42 | #define NVGPU_DBG_REG_OP_TYPE_GLOBAL (0x00000000) | ||
43 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX (0x00000001) | ||
44 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_TPC (0x00000002) | ||
45 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_SM (0x00000004) | ||
46 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_CROP (0x00000008) | ||
47 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_ZROP (0x00000010) | ||
48 | /*#define NVGPU_DBG_REG_OP_TYPE_FB (0x00000020)*/ | ||
49 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_QUAD (0x00000040) | ||
50 | |||
51 | /* valid status values */ | ||
52 | #define NVGPU_DBG_REG_OP_STATUS_SUCCESS (0x00000000) | ||
53 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_OP (0x00000001) | ||
54 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_TYPE (0x00000002) | ||
55 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_OFFSET (0x00000004) | ||
56 | #define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP (0x00000008) | ||
57 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK (0x00000010) | ||
58 | |||
59 | struct nvgpu_dbg_reg_op { | ||
60 | __u8 op; | ||
61 | __u8 type; | ||
62 | __u8 status; | ||
63 | __u8 quad; | ||
64 | __u32 group_mask; | ||
65 | __u32 sub_group_mask; | ||
66 | __u32 offset; | ||
67 | __u32 value_lo; | ||
68 | __u32 value_hi; | ||
69 | __u32 and_n_mask_lo; | ||
70 | __u32 and_n_mask_hi; | ||
71 | }; | ||
72 | |||
27 | struct regop_offset_range { | 73 | struct regop_offset_range { |
28 | u32 base:24; | 74 | u32 base:24; |
29 | u32 count:8; | 75 | u32 count:8; |
30 | }; | 76 | }; |
31 | 77 | ||
32 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | 78 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, |
33 | struct nvgpu_dbg_gpu_reg_op *ops, | 79 | struct nvgpu_dbg_reg_op *ops, |
34 | u64 num_ops); | 80 | u64 num_ops); |
35 | 81 | ||
36 | /* turn seriously unwieldy names -> something shorter */ | 82 | /* turn seriously unwieldy names -> something shorter */ |
37 | #define REGOP(x) NVGPU_DBG_GPU_REG_OP_##x | 83 | #define REGOP(x) NVGPU_DBG_REG_OP_##x |
38 | 84 | ||
39 | bool reg_op_is_gr_ctx(u8 type); | 85 | bool reg_op_is_gr_ctx(u8 type); |
40 | bool reg_op_is_read(u8 op); | 86 | bool reg_op_is_read(u8 op); |