gpu: nvgpu: add HAL for regops

Bug 1500195

Change-Id: I5545d1a95a58e7daa5a74cc20f3fc6828774fc42
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/488507
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 9 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
index 23b4865b..808e8bbe 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
@@ -19,6 +19,13 @@
 #ifndef __REGOPS_GK20A_H_
 #define __REGOPS_GK20A_H_
 
+#include <linux/nvhost_dbg_gpu_ioctl.h>
+
+struct regop_offset_range {
+        u32 base:24;
+        u32 count:8;
+};
+
 int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
                       struct nvhost_dbg_gpu_reg_op *ops,
                       u64 num_ops);
@@ -26,7 +33,6 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 /* turn seriously unwieldy names -> something shorter */
 #define REGOP(x) NVHOST_DBG_GPU_REG_OP_##x
 
-
 static inline bool reg_op_is_gr_ctx(u8 type)
 {
         return  type == REGOP(TYPE_GR_CTX) ||
@@ -42,6 +48,7 @@ static inline bool reg_op_is_read(u8 op)
                 op == REGOP(READ_64) ;
 }
 
-bool is_bar0_global_offset_whitelisted_gk20a(u32 offset);
+bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset);
 
+void gk20a_init_regops(struct gpu_ops *gops);
 #endif /* __REGOPS_GK20A_H_ */