diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 22:39:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-09 21:26:04 -0400 |
commit | dd739fcb039d51606e9a5454ec0aab17bcb01965 (patch) | |
tree | 806ba8575d146367ad1be00086ca0cdae35a6b28 /drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |
parent | 7e66f2a63d4855e763fa768047dfc32f6f96b771 (diff) |
gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/regops_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 60162f9d..5b9f973b 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -72,7 +72,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
72 | bool skip_read_lo, skip_read_hi; | 72 | bool skip_read_lo, skip_read_hi; |
73 | bool ok; | 73 | bool ok; |
74 | 74 | ||
75 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); | 75 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " "); |
76 | 76 | ||
77 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | 77 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); |
78 | 78 | ||
@@ -108,7 +108,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
108 | case REGOP(READ_32): | 108 | case REGOP(READ_32): |
109 | ops[i].value_hi = 0; | 109 | ops[i].value_hi = 0; |
110 | ops[i].value_lo = gk20a_readl(g, ops[i].offset); | 110 | ops[i].value_lo = gk20a_readl(g, ops[i].offset); |
111 | gk20a_dbg(gpu_dbg_gpu_dbg, "read_32 0x%08x from 0x%08x", | 111 | nvgpu_log(g, gpu_dbg_gpu_dbg, "read_32 0x%08x from 0x%08x", |
112 | ops[i].value_lo, ops[i].offset); | 112 | ops[i].value_lo, ops[i].offset); |
113 | 113 | ||
114 | break; | 114 | break; |
@@ -118,7 +118,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
118 | ops[i].value_hi = | 118 | ops[i].value_hi = |
119 | gk20a_readl(g, ops[i].offset + 4); | 119 | gk20a_readl(g, ops[i].offset + 4); |
120 | 120 | ||
121 | gk20a_dbg(gpu_dbg_gpu_dbg, "read_64 0x%08x:%08x from 0x%08x", | 121 | nvgpu_log(g, gpu_dbg_gpu_dbg, "read_64 0x%08x:%08x from 0x%08x", |
122 | ops[i].value_hi, ops[i].value_lo, | 122 | ops[i].value_hi, ops[i].value_lo, |
123 | ops[i].offset); | 123 | ops[i].offset); |
124 | break; | 124 | break; |
@@ -157,12 +157,12 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
157 | 157 | ||
158 | /* now update first 32bits */ | 158 | /* now update first 32bits */ |
159 | gk20a_writel(g, ops[i].offset, data32_lo); | 159 | gk20a_writel(g, ops[i].offset, data32_lo); |
160 | gk20a_dbg(gpu_dbg_gpu_dbg, "Wrote 0x%08x to 0x%08x ", | 160 | nvgpu_log(g, gpu_dbg_gpu_dbg, "Wrote 0x%08x to 0x%08x ", |
161 | data32_lo, ops[i].offset); | 161 | data32_lo, ops[i].offset); |
162 | /* if desired, update second 32bits */ | 162 | /* if desired, update second 32bits */ |
163 | if (ops[i].op == REGOP(WRITE_64)) { | 163 | if (ops[i].op == REGOP(WRITE_64)) { |
164 | gk20a_writel(g, ops[i].offset + 4, data32_hi); | 164 | gk20a_writel(g, ops[i].offset + 4, data32_hi); |
165 | gk20a_dbg(gpu_dbg_gpu_dbg, "Wrote 0x%08x to 0x%08x ", | 165 | nvgpu_log(g, gpu_dbg_gpu_dbg, "Wrote 0x%08x to 0x%08x ", |
166 | data32_hi, ops[i].offset + 4); | 166 | data32_hi, ops[i].offset + 4); |
167 | 167 | ||
168 | } | 168 | } |
@@ -189,7 +189,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
189 | } | 189 | } |
190 | 190 | ||
191 | clean_up: | 191 | clean_up: |
192 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | 192 | nvgpu_log(g, gpu_dbg_gpu_dbg, "ret=%d", err); |
193 | return err; | 193 | return err; |
194 | 194 | ||
195 | } | 195 | } |
@@ -395,7 +395,7 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
395 | } | 395 | } |
396 | } | 396 | } |
397 | 397 | ||
398 | gk20a_dbg(gpu_dbg_gpu_dbg, "ctx_wrs:%d ctx_rds:%d", | 398 | nvgpu_log(g, gpu_dbg_gpu_dbg, "ctx_wrs:%d ctx_rds:%d", |
399 | *ctx_wr_count, *ctx_rd_count); | 399 | *ctx_wr_count, *ctx_rd_count); |
400 | 400 | ||
401 | return ok; | 401 | return ok; |