gpu: nvgpu: Correction in allow_all flag usage

The allow_all flag is used to avoid any kind of register's
offset being validate when called through regops. but the
current implementation was flawed. It printed error messages
and set the status of each operation invalid, even when
allow_all was set.

Change-Id: Ie5a70a3cdc2368715731cf1c9cd771fdcf6b0d57
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/723830
(cherry picked from commit 4483ef020ff5f0fabc83b1226376b02d42bd1d75)
Reviewed-on: http://git-master/r/753282
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 8 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index b1c25ac9..1696f759 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -405,7 +405,8 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
 
         ok = validate_reg_ops(dbg_s,
                               &ctx_rd_count, &ctx_wr_count,
-                              ops, num_ops) || g->allow_all;
+                              ops, num_ops);
+
         if (!ok) {
                 dev_err(dbg_s->dev, "invalid op(s)");
                 err = -EINVAL;
@@ -678,6 +679,7 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
         u32 i;
         int err;
         bool ok = true;
+        struct gk20a *g = dbg_s->g;
 
         /* keep going until the end so every op can get
          * a separate error code if needed */
@@ -693,8 +695,11 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
                                 (*ctx_wr_count)++;
                 }
 
-                err = validate_reg_op_offset(dbg_s, &ops[i]);
-                ok &= !err;
+                /* if "allow_all" flag enabled, dont validate offset */
+                if (!g->allow_all) {
+                        err = validate_reg_op_offset(dbg_s, &ops[i]);
+                        ok &= !err;
+                }
         }
 
         gk20a_dbg(gpu_dbg_gpu_dbg, "ctx_wrs:%d ctx_rds:%d",