diff options
author | Mayank Kaushik <mkaushik@nvidia.com> | 2014-09-25 20:21:24 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:57 -0400 |
commit | 1ee103adf30c14efef932faedc6b1bb226f7139b (patch) | |
tree | cecd392c75e937767ba2e4b211cbfe28bca1e926 /drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |
parent | aec94d809348e8ff9a900c2a38456d7217c86728 (diff) |
gpu: nvgpu: create a hal function for smpc war
Create a HAL function for applying the SMPC workaround.The workaround
is only needed on gk20a, and not on gm20b.
Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/539187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/regops_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 7adb458b..d9984e03 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -757,6 +757,42 @@ int gk20a_get_qctl_whitelist_ranges_count(void) | |||
757 | return gk20a_qctl_whitelist_ranges_count; | 757 | return gk20a_qctl_whitelist_ranges_count; |
758 | } | 758 | } |
759 | 759 | ||
760 | int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
761 | { | ||
762 | /* The following regops are a hack/war to make up for the fact that we | ||
763 | * just scribbled into the ctxsw image w/o really knowing whether | ||
764 | * it was already swapped out in/out once or not, etc. | ||
765 | */ | ||
766 | struct nvgpu_dbg_gpu_reg_op ops[4]; | ||
767 | int i; | ||
768 | for (i = 0; i < ARRAY_SIZE(ops); i++) { | ||
769 | ops[i].op = REGOP(WRITE_32); | ||
770 | ops[i].type = REGOP(TYPE_GR_CTX); | ||
771 | ops[i].status = REGOP(STATUS_SUCCESS); | ||
772 | ops[i].value_hi = 0; | ||
773 | ops[i].and_n_mask_lo = 0; | ||
774 | ops[i].and_n_mask_hi = 0; | ||
775 | } | ||
776 | |||
777 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/ | ||
778 | ops[0].offset = 0x00419e08; | ||
779 | ops[0].value_lo = 0x1d; | ||
780 | |||
781 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */ | ||
782 | ops[1].offset = 0x00419e58; | ||
783 | ops[1].value_lo = 0x1; | ||
784 | |||
785 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */ | ||
786 | ops[2].offset = 0x00419e68; | ||
787 | ops[2].value_lo = 0xaaaa; | ||
788 | |||
789 | /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */ | ||
790 | ops[3].offset = 0x00419f40; | ||
791 | ops[3].value_lo = 0x18; | ||
792 | |||
793 | return dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops)); | ||
794 | } | ||
795 | |||
760 | void gk20a_init_regops(struct gpu_ops *gops) | 796 | void gk20a_init_regops(struct gpu_ops *gops) |
761 | { | 797 | { |
762 | gops->regops.get_global_whitelist_ranges = | 798 | gops->regops.get_global_whitelist_ranges = |
@@ -788,4 +824,7 @@ void gk20a_init_regops(struct gpu_ops *gops) | |||
788 | gk20a_get_qctl_whitelist_ranges; | 824 | gk20a_get_qctl_whitelist_ranges; |
789 | gops->regops.get_qctl_whitelist_ranges_count = | 825 | gops->regops.get_qctl_whitelist_ranges_count = |
790 | gk20a_get_qctl_whitelist_ranges_count; | 826 | gk20a_get_qctl_whitelist_ranges_count; |
827 | |||
828 | gops->regops.apply_smpc_war = | ||
829 | gk20a_apply_smpc_war; | ||
791 | } | 830 | } |