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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-05-01 14:02:33 -0400
committerSai Gurrappadi <sgurrappadi@nvidia.com>2017-05-01 18:17:56 -0400
commit4d1237f132163cb0a397a5407570377e77d70b1b (patch)
tree180201e299f3ad707270253799ed2cff75fc1223 /drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
parent966d62e53f70caf2ffa3083ffe59712c8c09b7c5 (diff)
Revert "gpu: nvgpu: Dump error on priv ring intr"
This reverts commit 69d7652aaa9cf94873cccae13c7b6f6a4eb224af. Bug 1918711 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: Ie28c668729c4956f18e6fa3c820f476d2e4424a4 Reviewed-on: http://git-master/r/1473044 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index 239d8efd..1584ffda 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -80,7 +80,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
80 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); 80 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
81 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); 81 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
82 82
83 nvgpu_err(g, "ringmaster intr status0: 0x%08x," 83 gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x,"
84 "status1: 0x%08x", status0, status1); 84 "status1: 0x%08x", status0, status1);
85 85
86 if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 || 86 if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 ||
@@ -90,7 +90,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
90 } 90 }
91 91
92 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { 92 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
93 nvgpu_err(g, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", 93 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
94 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), 94 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
95 gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), 95 gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
96 gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), 96 gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
@@ -99,7 +99,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
99 99
100 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { 100 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
101 if (status1 & BIT(gpc)) { 101 if (status1 & BIT(gpc)) {
102 nvgpu_err(g, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, 102 gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
103 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride), 103 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
104 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride), 104 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
105 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride), 105 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),