gpu: nvgpu: Move clk bypass div code to clk init

Clock bypass divider was changed just before resetting priv ring.
Move the code to a new clk op instead so that it is executed only on
gk20a.

Change-Id: Ic8084a4a5fac23770f50b50f910ced2543ba0f28
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/764970
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 0 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index d11cff06..d19702bb 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -22,21 +22,12 @@
 #include "hw_mc_gk20a.h"
 #include "hw_pri_ringmaster_gk20a.h"
 #include "hw_pri_ringstation_sys_gk20a.h"
-#include "hw_trim_gk20a.h"
 
 void gk20a_reset_priv_ring(struct gk20a *g)
 {
-        u32 data;
-
         if (tegra_platform_is_linsim())
                 return;
 
-        data = gk20a_readl(g, trim_sys_gpc2clk_out_r());
-        data = set_field(data,
-                        trim_sys_gpc2clk_out_bypdiv_m(),
-                        trim_sys_gpc2clk_out_bypdiv_f(0));
-        gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
-
         gk20a_reset(g, mc_enable_priv_ring_enabled_f());
 
         if (g->ops.clock_gating.slcg_priring_load_gating_prod)