summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
diff options
context:
space:
mode:
authorSeema Khowala <seemaj@nvidia.com>2017-02-24 19:14:03 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-07 03:10:44 -0500
commit35f0cf0efefe4a64ee25a5b118338b15e552dcb0 (patch)
treec23c4a62e154d83d1558d9d50681cf5bfd1b1899 /drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
parentd6ff5ef649ead7cf7caded5c7742efd7ad569a8a (diff)
gpu: nvgpu: change stall intr handling order
-Handle pbus and priv stall interrupts first. In general critical interrupts should be handled before any other non critical ones. -Dump info enabled with gpu_dbg_intr if priv_ring interrupt is flagged by fmodel. JIRA NVGPU-25 Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1311273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index a44df1e8..90bd95ac 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -76,8 +76,6 @@ void gk20a_priv_ring_isr(struct gk20a *g)
76 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 76 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
77 struct gk20a_platform *platform = dev_get_drvdata(g->dev); 77 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
78 78
79 if (platform->is_fmodel)
80 return;
81 79
82 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); 80 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
83 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); 81 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
@@ -90,7 +88,6 @@ void gk20a_priv_ring_isr(struct gk20a *g)
90 pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) { 88 pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
91 gk20a_reset_priv_ring(g); 89 gk20a_reset_priv_ring(g);
92 } 90 }
93
94 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { 91 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
95 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", 92 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
96 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), 93 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
@@ -109,6 +106,9 @@ void gk20a_priv_ring_isr(struct gk20a *g)
109 } 106 }
110 } 107 }
111 108
109 if (platform->is_fmodel)
110 return;
111
112 cmd = gk20a_readl(g, pri_ringmaster_command_r()); 112 cmd = gk20a_readl(g, pri_ringmaster_command_r());
113 cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), 113 cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
114 pri_ringmaster_command_cmd_ack_interrupt_f()); 114 pri_ringmaster_command_cmd_ack_interrupt_f());