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authorDeepak Goyal <dgoyal@nvidia.com>2016-11-23 23:42:02 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-01-18 19:46:27 -0500
commiteba4aba00c54485e76e8d8adf5430abd9d10fe79 (patch)
tree28d2f3dfafc30bd00772213931eddb2fb1d85daf /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
parent911dcedb489ebef5758e5533f73e8653cc7770b7 (diff)
nvgpu: pmu: Add support for new PMU ucode.
-GV11B PMU ucode is added in nvgpu supported ucodes. -PMU INIT msg structure(v4) is added JIRA GV11B-30 Change-Id: Ifced87b1ca2692c277ae11f562cb36b328da3fe4 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1259274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index daa050af..b6f2e013 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -38,6 +38,7 @@
38 38
39#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) 39#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
40 40
41#define APP_VERSION_NC_3 21548462
41#define APP_VERSION_NC_2 20429989 42#define APP_VERSION_NC_2 20429989
42#define APP_VERSION_NC_1 20313802 43#define APP_VERSION_NC_1 20313802
43#define APP_VERSION_NC_0 20360931 44#define APP_VERSION_NC_0 20360931
@@ -264,6 +265,7 @@ struct pmu_init_msg_pmu_v2 {
264 u8 dummy[18]; 265 u8 dummy[18];
265}; 266};
266 267
268#define PMU_QUEUE_COUNT_FOR_V4 5
267#define PMU_QUEUE_COUNT_FOR_V3 3 269#define PMU_QUEUE_COUNT_FOR_V3 3
268#define PMU_QUEUE_HPQ_IDX_FOR_V3 0 270#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
269#define PMU_QUEUE_LPQ_IDX_FOR_V3 1 271#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
@@ -282,11 +284,26 @@ struct pmu_init_msg_pmu_v3 {
282 u8 dummy[18]; 284 u8 dummy[18];
283}; 285};
284 286
287struct pmu_init_msg_pmu_v4 {
288 u8 msg_type;
289 u8 queue_index[PMU_QUEUE_COUNT_FOR_V4];
290 u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
291 u16 queue_offset;
292
293 u16 sw_managed_area_offset;
294 u16 sw_managed_area_size;
295
296 u16 os_debug_entry_point;
297
298 u8 dummy[18];
299};
300
285union pmu_init_msg_pmu { 301union pmu_init_msg_pmu {
286 struct pmu_init_msg_pmu_v0 v0; 302 struct pmu_init_msg_pmu_v0 v0;
287 struct pmu_init_msg_pmu_v1 v1; 303 struct pmu_init_msg_pmu_v1 v1;
288 struct pmu_init_msg_pmu_v2 v2; 304 struct pmu_init_msg_pmu_v2 v2;
289 struct pmu_init_msg_pmu_v3 v3; 305 struct pmu_init_msg_pmu_v3 v3;
306 struct pmu_init_msg_pmu_v4 v4;
290}; 307};
291 308
292struct pmu_init_msg { 309struct pmu_init_msg {
@@ -296,6 +313,7 @@ struct pmu_init_msg {
296 struct pmu_init_msg_pmu_v0 pmu_init_v0; 313 struct pmu_init_msg_pmu_v0 pmu_init_v0;
297 struct pmu_init_msg_pmu_v2 pmu_init_v2; 314 struct pmu_init_msg_pmu_v2 pmu_init_v2;
298 struct pmu_init_msg_pmu_v3 pmu_init_v3; 315 struct pmu_init_msg_pmu_v3 pmu_init_v3;
316 struct pmu_init_msg_pmu_v4 pmu_init_v4;
299 }; 317 };
300}; 318};
301 319