diff options
author | Supriya <ssharatkumar@nvidia.com> | 2014-06-13 03:14:27 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:14 -0400 |
commit | b7793a493a1fa292a22d5ce84c43ee342b9824b2 (patch) | |
tree | 963d128e317d319d2f53aff96420aec17b732bf6 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |
parent | c32ac10b0bba400c1e83540a20c5ca210fa48613 (diff) |
nvgpu: Host side changes to support HS mode
GM20B changes in PMU boot sequence to support booting in
HS mode and LS mode
Bug 1509680
Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/423140
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 2843d483..e9567e14 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -51,6 +51,8 @@ | |||
51 | /* Mapping between AP_CTRLs and Idle counters */ | 51 | /* Mapping between AP_CTRLs and Idle counters */ |
52 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | 52 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) |
53 | 53 | ||
54 | #define APP_VERSION_GM20B_1 18547257 | ||
55 | #define APP_VERSION_GM20B 17615280 | ||
54 | #define APP_VERSION_2 18542378 | 56 | #define APP_VERSION_2 18542378 |
55 | #define APP_VERSION_1 17997577 | 57 | #define APP_VERSION_1 17997577 |
56 | #define APP_VERSION_0 16856675 | 58 | #define APP_VERSION_0 16856675 |
@@ -1058,6 +1060,8 @@ struct pmu_gk20a { | |||
1058 | }; | 1060 | }; |
1059 | unsigned long perfmon_events_cnt; | 1061 | unsigned long perfmon_events_cnt; |
1060 | bool perfmon_sampling_enabled; | 1062 | bool perfmon_sampling_enabled; |
1063 | u8 pmu_mode; /*Added for GM20b, and ACR*/ | ||
1064 | u32 falcon_id; | ||
1061 | }; | 1065 | }; |
1062 | 1066 | ||
1063 | int gk20a_init_pmu_support(struct gk20a *g); | 1067 | int gk20a_init_pmu_support(struct gk20a *g); |
@@ -1086,5 +1090,16 @@ int gk20a_pmu_debugfs_init(struct platform_device *dev); | |||
1086 | void gk20a_pmu_reset_load_counters(struct gk20a *g); | 1090 | void gk20a_pmu_reset_load_counters(struct gk20a *g); |
1087 | void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, | 1091 | void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, |
1088 | u32 *total_cycles); | 1092 | u32 *total_cycles); |
1089 | 1093 | void gk20a_init_pmu_ops(struct gpu_ops *gops); | |
1094 | |||
1095 | void pmu_copy_to_dmem(struct pmu_gk20a *pmu, | ||
1096 | u32 dst, u8 *src, u32 size, u8 port); | ||
1097 | void pmu_copy_from_dmem(struct pmu_gk20a *pmu, | ||
1098 | u32 src, u8 *dst, u32 size, u8 port); | ||
1099 | int pmu_reset(struct pmu_gk20a *pmu); | ||
1100 | int gk20a_init_pmu(struct pmu_gk20a *pmu); | ||
1101 | void pmu_dump_falcon_stats(struct pmu_gk20a *pmu); | ||
1102 | void gk20a_remove_pmu_support(struct pmu_gk20a *pmu); | ||
1103 | void pmu_setup_hw(struct work_struct *work); | ||
1104 | void pmu_seq_init(struct pmu_gk20a *pmu); | ||
1090 | #endif /*__PMU_GK20A_H__*/ | 1105 | #endif /*__PMU_GK20A_H__*/ |