diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2015-08-06 04:26:27 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-08-13 11:08:43 -0400 |
commit | aef94648e256760806a9a38bb017a793e44a82ca (patch) | |
tree | e65807c2ddb3f8dee396a31f22defa8df9eb8e17 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |
parent | 77e608d528b85d9b63bef90606afbcd8504e16d1 (diff) |
gpu: nvgpu: T186 perfmon ID update
Change-Id: Iec6aac4027c8079d10e6d09bb145fa7a37d1679b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/779696
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 34 |
1 files changed, 3 insertions, 31 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 6676c2e5..3dd16ec4 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -428,40 +428,12 @@ struct pmu_ucode_desc { | |||
428 | }; | 428 | }; |
429 | 429 | ||
430 | #define PMU_UNIT_REWIND (0x00) | 430 | #define PMU_UNIT_REWIND (0x00) |
431 | #define PMU_UNIT_I2C (0x01) | 431 | #define PMU_UNIT_PG (0x03) |
432 | #define PMU_UNIT_SEQ (0x02) | ||
433 | #define PMU_UNIT_PG (0x03) | ||
434 | #define PMU_UNIT_AVAILABLE1 (0x04) | ||
435 | #define PMU_UNIT_AVAILABLE2 (0x05) | ||
436 | #define PMU_UNIT_MEM (0x06) | ||
437 | #define PMU_UNIT_INIT (0x07) | 432 | #define PMU_UNIT_INIT (0x07) |
438 | #define PMU_UNIT_FBBA (0x08) | ||
439 | #define PMU_UNIT_DIDLE (0x09) | ||
440 | #define PMU_UNIT_ACR (0x0A) | 433 | #define PMU_UNIT_ACR (0x0A) |
441 | #define PMU_UNIT_AVAILABLE4 (0x0B) | 434 | #define PMU_UNIT_PERFMON_T18X (0x11) |
442 | #define PMU_UNIT_HDCP_MAIN (0x0C) | ||
443 | #define PMU_UNIT_HDCP_V (0x0D) | ||
444 | #define PMU_UNIT_HDCP_SRM (0x0E) | ||
445 | #define PMU_UNIT_NVDPS (0x0F) | ||
446 | #define PMU_UNIT_DEINIT (0x10) | ||
447 | #define PMU_UNIT_AVAILABLE5 (0x11) | ||
448 | #define PMU_UNIT_PERFMON (0x12) | 435 | #define PMU_UNIT_PERFMON (0x12) |
449 | #define PMU_UNIT_FAN (0x13) | 436 | #define PMU_UNIT_RC (0x1F) |
450 | #define PMU_UNIT_PBI (0x14) | ||
451 | #define PMU_UNIT_ISOBLIT (0x15) | ||
452 | #define PMU_UNIT_DETACH (0x16) | ||
453 | #define PMU_UNIT_DISP (0x17) | ||
454 | #define PMU_UNIT_HDCP (0x18) | ||
455 | #define PMU_UNIT_REGCACHE (0x19) | ||
456 | #define PMU_UNIT_SYSMON (0x1A) | ||
457 | #define PMU_UNIT_THERM (0x1B) | ||
458 | #define PMU_UNIT_PMGR (0x1C) | ||
459 | #define PMU_UNIT_PERF (0x1D) | ||
460 | #define PMU_UNIT_PCM (0x1E) | ||
461 | #define PMU_UNIT_RC (0x1F) | ||
462 | #define PMU_UNIT_NULL (0x20) | ||
463 | #define PMU_UNIT_LOGGER (0x21) | ||
464 | #define PMU_UNIT_SMBPBI (0x22) | ||
465 | #define PMU_UNIT_END (0x23) | 437 | #define PMU_UNIT_END (0x23) |
466 | 438 | ||
467 | #define PMU_UNIT_TEST_START (0xFE) | 439 | #define PMU_UNIT_TEST_START (0xFE) |