diff options
| author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-09-28 18:26:23 -0400 |
|---|---|---|
| committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-29 16:15:15 -0400 |
| commit | ab93322b25c9dd6058fac6523f41571d77eeaeb9 (patch) | |
| tree | ad403ae2dea3fe8842d0c60076ee59c4f5bcb95c /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |
| parent | 39e8bff2fc02b4037dc925076e5f42f6519101eb (diff) | |
gpu: nvgpu: Add CDE bits in FECS header
In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.
Bug 200096226
Change-Id: I8a8deaf6fb91f4bbceacd491db7eb6f7bca5001b
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/804625
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
0 files changed, 0 insertions, 0 deletions