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authorDeepak Nibade <dnibade@nvidia.com>2017-01-24 08:30:42 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-22 07:15:02 -0500
commit8ee3aa4b3175d8d27e57a0f5d5e2cdf3d78a4a58 (patch)
tree505dfd2ea2aca2f1cbdb254baee980862d21e04d /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
parent1f855af63fdd31fe3dcfee75f4f5f9b62f30d87e (diff)
gpu: nvgpu: use common nvgpu mutex/spinlock APIs
Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index e4513457..c1583eab 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -136,7 +136,7 @@ struct pmu_queue {
136 u32 mutex_id; 136 u32 mutex_id;
137 u32 mutex_lock; 137 u32 mutex_lock;
138 /* used by sw, for LPQ/HPQ queue */ 138 /* used by sw, for LPQ/HPQ queue */
139 struct mutex mutex; 139 struct nvgpu_mutex mutex;
140 140
141 /* current write position */ 141 /* current write position */
142 u32 position; 142 u32 position;
@@ -334,8 +334,8 @@ struct pmu_gk20a {
334 struct pmu_mutex *mutex; 334 struct pmu_mutex *mutex;
335 u32 mutex_cnt; 335 u32 mutex_cnt;
336 336
337 struct mutex pmu_copy_lock; 337 struct nvgpu_mutex pmu_copy_lock;
338 struct mutex pmu_seq_lock; 338 struct nvgpu_mutex pmu_seq_lock;
339 339
340 struct nvgpu_allocator dmem; 340 struct nvgpu_allocator dmem;
341 341
@@ -355,8 +355,8 @@ struct pmu_gk20a {
355 355
356#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1 /* msec */ 356#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1 /* msec */
357 struct work_struct pg_init; 357 struct work_struct pg_init;
358 struct mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */ 358 struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */
359 struct mutex elpg_mutex; /* protect elpg enable/disable */ 359 struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */
360 int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */ 360 int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
361 361
362 union { 362 union {
@@ -375,7 +375,7 @@ struct pmu_gk20a {
375 u32 load_shadow; 375 u32 load_shadow;
376 u32 load_avg; 376 u32 load_avg;
377 377
378 struct mutex isr_mutex; 378 struct nvgpu_mutex isr_mutex;
379 bool isr_enabled; 379 bool isr_enabled;
380 380
381 bool zbc_ready; 381 bool zbc_ready;