gpu: nvgpu: reorganize PMU FB alloc/free

Moved PMU FB access related code from pmu_gk20a.c to
"drivers/gpu/nvgpu/common/pmu/pmu.c" file
- Prepended with nvgpu_ for global functions & replaced
wherever used.

JIRA NVGPU-56
JIRA NVGPU-94

Change-Id: I42bfd9d216e6b35672a9738f01302d954b32b69e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1480551
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 0 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 1c29b380..1d2e20e6 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -57,12 +57,6 @@ struct nvgpu_firmware;
 #define PMU_PGENG_GR_BUFFER_IDX_ZBC     (1)
 #define PMU_PGENG_GR_BUFFER_IDX_FECS    (2)
 
-struct pmu_surface {
-        struct nvgpu_mem vidmem_desc;
-        struct nvgpu_mem sysmem_desc;
-        struct flcn_mem_desc_v0 params;
-};
-
 #define PMU_PG_IDLE_THRESHOLD_SIM               1000
 #define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM  4000000
 /* TBD: QT or else ? */
@@ -154,13 +148,6 @@ int gk20a_pmu_reset(struct gk20a *g);
 int pmu_idle(struct nvgpu_pmu *pmu);
 int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable);
 
-void gk20a_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem);
-void gk20a_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
-                struct flcn_mem_desc_v0 *fb);
-int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
-                u32 size);
-int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
-                u32 size);
 bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
 
 int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu);