diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-06-13 05:51:56 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-15 14:18:51 -0400 |
commit | 77e2cbab237637f71367df25384164b8c936a31a (patch) | |
tree | 64ccc10c4c6aa3eddbcac1d697d50b860247bf57 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |
parent | 7d16f7e52c0f8ce8604e992a617a3f98545fcf07 (diff) |
gpu: nvgpu: reorganize PMU perfmon
-Moved perfmon code from pmu_gk20a.c to
"drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c" file
-Moved below related methods
perfmon init,
start/stop sampling,
load counter read/write/reset,
perfmon event handler
- prepend with nvgpu_ for perfmon global methods
by replacing gk20a_
JURA NVGPU-56
JURA NVGPU-98
Change-Id: Idbcdf63ebd76da170e609cc401b320a42110cd7b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1501418
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 4a1609d6..a88bc404 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -38,7 +38,7 @@ u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id); | |||
38 | 38 | ||
39 | void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); | 39 | void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); |
40 | 40 | ||
41 | int gk20a_pmu_perfmon_enable(struct gk20a *g, bool enable); | 41 | void gk20a_pmu_init_perfmon_counter(struct gk20a *g); |
42 | 42 | ||
43 | void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id); | 43 | void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id); |
44 | 44 | ||
@@ -51,11 +51,9 @@ int gk20a_pmu_queue_tail(struct nvgpu_pmu *pmu, struct pmu_queue *queue, | |||
51 | u32 *tail, bool set); | 51 | u32 *tail, bool set); |
52 | void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set); | 52 | void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set); |
53 | 53 | ||
54 | int gk20a_pmu_load_norm(struct gk20a *g, u32 *load); | 54 | u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id); |
55 | int gk20a_pmu_load_update(struct gk20a *g); | 55 | void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id); |
56 | void gk20a_pmu_reset_load_counters(struct gk20a *g); | 56 | |
57 | void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, | ||
58 | u32 *total_cycles); | ||
59 | void gk20a_init_pmu_ops(struct gpu_ops *gops); | 57 | void gk20a_init_pmu_ops(struct gpu_ops *gops); |
60 | 58 | ||
61 | void pmu_copy_to_dmem(struct nvgpu_pmu *pmu, | 59 | void pmu_copy_to_dmem(struct nvgpu_pmu *pmu, |
@@ -81,7 +79,4 @@ int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable); | |||
81 | 79 | ||
82 | bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos); | 80 | bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos); |
83 | 81 | ||
84 | int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu); | ||
85 | int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu); | ||
86 | |||
87 | #endif /*__PMU_GK20A_H__*/ | 82 | #endif /*__PMU_GK20A_H__*/ |