diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2018-08-22 00:27:01 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 20:46:51 -0400 |
commit | 74639b444251d7adc222400625eb59a3d53d0c0a (patch) | |
tree | 19373fbe8ee522863c990fdfa0db24e6474f5167 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |
parent | e3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c (diff) |
gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL
In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h
JIRA-597
Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index d9c53c28..ee7ee8c7 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -67,9 +67,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu); | |||
67 | void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); | 67 | void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); |
68 | void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); | 68 | void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); |
69 | 69 | ||
70 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); | 70 | void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); |
71 | int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, | ||
72 | void *var, u8 val); | ||
73 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | 71 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, |
74 | void *param, u32 handle, u32 status); | 72 | void *param, u32 handle, u32 status); |
75 | void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 73 | void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |