gpu: nvgpu: Rewrite PMU boot-up sequence

Rewrite PMU boot sequence as a state machine. At PMU power-up send
initial messages, and reset state machine. At each reply from PMU,
do the next stage of PMU boot and set state.

As now PMU and FECS boot are independent, we need to ensure engine
idle before saving ZBC.

Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410205

1 files changed, 11 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 8aaea33f..2843d483 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -987,6 +987,14 @@ struct pmu_pg_stats {
 #define PMU_FALCON_REG_RSVD2            (31)
 #define PMU_FALCON_REG_SIZE             (32)
 
+/* Choices for pmu_state */
+#define PMU_STATE_OFF                   0 /* PMU is off */
+#define PMU_STATE_STARTING              1 /* PMU is booting */
+#define PMU_STATE_ELPG_BOOTED           2 /* ELPG is initialized */
+#define PMU_STATE_LOADING_PG_BUF        3 /* Loading PG buf */
+#define PMU_STATE_LOADING_ZBC           4 /* Loading ZBC buf */
+#define PMU_STATE_STARTED               5 /* Fully unitialized */
+
 struct pmu_gk20a {
 
         struct gk20a *g;
@@ -1022,9 +1030,9 @@ struct pmu_gk20a {
 
         u32 stat_dmem_offset;
 
-        bool elpg_ready;
         u32 elpg_stat;
-        wait_queue_head_t pg_wq;
+
+        int pmu_state;
 
 #define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC        1 /* msec */
         struct work_struct pg_init;
@@ -1053,7 +1061,7 @@ struct pmu_gk20a {
 };
 
 int gk20a_init_pmu_support(struct gk20a *g);
-int gk20a_init_pmu_setup_hw2(struct gk20a *g);
+int gk20a_init_pmu_bind_fecs(struct gk20a *g);
 
 void gk20a_pmu_isr(struct gk20a *g);