gpu: nvgpu: moved & renamed "struct pmu_gk20a"

- Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved
to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/"

- Included header file "pmu.h" to dependent file &
removed "pmu_gk20a.h" include if its usage is not present.

- Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent
source & header files.

JIRA NVGPU-56

Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1479209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 18 insertions, 306 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index cfcf3947..3941d90f 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -24,14 +24,10 @@
 #include <linux/version.h>
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+#include <nvgpu/pmu.h>
 
 struct nvgpu_firmware;
 
-/* defined by pmu hw spec */
-#define GK20A_PMU_VA_SIZE               (512 * 1024 * 1024)
-#define GK20A_PMU_UCODE_SIZE_MAX        (256 * 1024)
-#define GK20A_PMU_SEQ_BUF_SIZE          4096
-
 #define ZBC_MASK(i)                     (~(~(0) << ((i)+1)) & 0xfffe)
 
 #define APP_VERSION_NC_3        21688026
@@ -56,127 +52,11 @@ struct nvgpu_firmware;
 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
 #define FUSE_GCPLEX_CONFIG_FUSE_0           0x2C8
 #endif
-#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R  6
-#define PMU_MODE_MISMATCH_STATUS_VAL        0xDEADDEAD
-
-enum {
-        GK20A_PMU_DMAIDX_UCODE          = 0,
-        GK20A_PMU_DMAIDX_VIRT           = 1,
-        GK20A_PMU_DMAIDX_PHYS_VID       = 2,
-        GK20A_PMU_DMAIDX_PHYS_SYS_COH   = 3,
-        GK20A_PMU_DMAIDX_PHYS_SYS_NCOH  = 4,
-        GK20A_PMU_DMAIDX_RSVD           = 5,
-        GK20A_PMU_DMAIDX_PELPG          = 6,
-        GK20A_PMU_DMAIDX_END            = 7
-};
-
-#define GK20A_PMU_TRACE_BUFSIZE     0x4000   /* 4K */
-#define GK20A_PMU_DMEM_BLKSIZE2         8
-
-#define GK20A_PMU_UCODE_NB_MAX_OVERLAY      32
-#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH  64
-
-struct pmu_ucode_desc {
-        u32 descriptor_size;
-        u32 image_size;
-        u32 tools_version;
-        u32 app_version;
-        char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
-        u32 bootloader_start_offset;
-        u32 bootloader_size;
-        u32 bootloader_imem_offset;
-        u32 bootloader_entry_point;
-        u32 app_start_offset;
-        u32 app_size;
-        u32 app_imem_offset;
-        u32 app_imem_entry;
-        u32 app_dmem_offset;
-        u32 app_resident_code_offset;  /* Offset from appStartOffset */
-        u32 app_resident_code_size;    /* Exact size of the resident code ( potentially contains CRC inside at the end ) */
-        u32 app_resident_data_offset;  /* Offset from appStartOffset */
-        u32 app_resident_data_size;    /* Exact size of the resident code ( potentially contains CRC inside at the end ) */
-        u32 nb_overlays;
-        struct {u32 start; u32 size;} load_ovl[GK20A_PMU_UCODE_NB_MAX_OVERLAY];
-        u32 compressed;
-};
-
-struct pmu_ucode_desc_v1 {
-        u32 descriptor_size;
-        u32 image_size;
-        u32 tools_version;
-        u32 app_version;
-        char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH];
-        u32 bootloader_start_offset;
-        u32 bootloader_size;
-        u32 bootloader_imem_offset;
-        u32 bootloader_entry_point;
-        u32 app_start_offset;
-        u32 app_size;
-        u32 app_imem_offset;
-        u32 app_imem_entry;
-        u32 app_dmem_offset;
-        u32 app_resident_code_offset;
-        u32 app_resident_code_size;
-        u32 app_resident_data_offset;
-        u32 app_resident_data_size;
-        u32 nb_imem_overlays;
-        u32 nb_dmem_overlays;
-        struct {u32 start; u32 size; } load_ovl[64];
-        u32 compressed;
-};
 
 #define PMU_PGENG_GR_BUFFER_IDX_INIT    (0)
 #define PMU_PGENG_GR_BUFFER_IDX_ZBC     (1)
 #define PMU_PGENG_GR_BUFFER_IDX_FECS    (2)
 
-struct pmu_gk20a;
-struct pmu_queue;
-
-struct pmu_queue {
-
-        /* used by hw, for BIOS/SMI queue */
-        u32 mutex_id;
-        u32 mutex_lock;
-        /* used by sw, for LPQ/HPQ queue */
-        struct nvgpu_mutex mutex;
-
-        /* current write position */
-        u32 position;
-        /* physical dmem offset where this queue begins */
-        u32 offset;
-        /* logical queue identifier */
-        u32 id;
-        /* physical queue index */
-        u32 index;
-        /* in bytes */
-        u32 size;
-
-        /* open-flag */
-        u32 oflag;
-        bool opened; /* opened implies locked */
-};
-
-struct pmu_mutex {
-        u32 id;
-        u32 index;
-        u32 ref_cnt;
-};
-
-#define PMU_MAX_NUM_SEQUENCES           (256)
-#define PMU_SEQ_BIT_SHIFT               (5)
-#define PMU_SEQ_TBL_SIZE        \
-                (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
-
-#define PMU_INVALID_SEQ_DESC            (~0)
-
-enum
-{
-        PMU_SEQ_STATE_FREE = 0,
-        PMU_SEQ_STATE_PENDING,
-        PMU_SEQ_STATE_USED,
-        PMU_SEQ_STATE_CANCELLED
-};
-
 struct pmu_payload {
         struct {
                 void *buf;
@@ -192,33 +72,6 @@ struct pmu_surface {
         struct flcn_mem_desc_v0 params;
 };
 
-typedef void (*pmu_callback)(struct gk20a *, struct pmu_msg *, void *, u32,
-        u32);
-
-struct pmu_sequence {
-        u8 id;
-        u32 state;
-        u32 desc;
-        struct pmu_msg *msg;
-        union {
-                struct pmu_allocation_v0 in_v0;
-                struct pmu_allocation_v1 in_v1;
-                struct pmu_allocation_v2 in_v2;
-                struct pmu_allocation_v3 in_v3;
-        };
-        struct nvgpu_mem *in_mem;
-        union {
-                struct pmu_allocation_v0 out_v0;
-                struct pmu_allocation_v1 out_v1;
-                struct pmu_allocation_v2 out_v2;
-                struct pmu_allocation_v3 out_v3;
-        };
-        struct nvgpu_mem *out_mem;
-        u8 *out_payload;
-        pmu_callback callback;
-        void* cb_params;
-};
-
 /*PG defines used by nvpgu-pmu*/
 struct pmu_pg_stats_data {
         u32 gating_cnt;
@@ -263,147 +116,6 @@ struct pmu_pg_stats_data {
 #define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT                    (200)
 /*PG defines used by nvpgu-pmu*/
 
-/* Falcon Register index */
-#define PMU_FALCON_REG_R0               (0)
-#define PMU_FALCON_REG_R1               (1)
-#define PMU_FALCON_REG_R2               (2)
-#define PMU_FALCON_REG_R3               (3)
-#define PMU_FALCON_REG_R4               (4)
-#define PMU_FALCON_REG_R5               (5)
-#define PMU_FALCON_REG_R6               (6)
-#define PMU_FALCON_REG_R7               (7)
-#define PMU_FALCON_REG_R8               (8)
-#define PMU_FALCON_REG_R9               (9)
-#define PMU_FALCON_REG_R10              (10)
-#define PMU_FALCON_REG_R11              (11)
-#define PMU_FALCON_REG_R12              (12)
-#define PMU_FALCON_REG_R13              (13)
-#define PMU_FALCON_REG_R14              (14)
-#define PMU_FALCON_REG_R15              (15)
-#define PMU_FALCON_REG_IV0              (16)
-#define PMU_FALCON_REG_IV1              (17)
-#define PMU_FALCON_REG_UNDEFINED        (18)
-#define PMU_FALCON_REG_EV               (19)
-#define PMU_FALCON_REG_SP               (20)
-#define PMU_FALCON_REG_PC               (21)
-#define PMU_FALCON_REG_IMB              (22)
-#define PMU_FALCON_REG_DMB              (23)
-#define PMU_FALCON_REG_CSW              (24)
-#define PMU_FALCON_REG_CCR              (25)
-#define PMU_FALCON_REG_SEC              (26)
-#define PMU_FALCON_REG_CTX              (27)
-#define PMU_FALCON_REG_EXCI             (28)
-#define PMU_FALCON_REG_RSVD0            (29)
-#define PMU_FALCON_REG_RSVD1            (30)
-#define PMU_FALCON_REG_RSVD2            (31)
-#define PMU_FALCON_REG_SIZE             (32)
-
-/* Choices for pmu_state */
-#define PMU_STATE_OFF                   0 /* PMU is off */
-#define PMU_STATE_STARTING              1 /* PMU is on, but not booted */
-#define PMU_STATE_INIT_RECEIVED         2 /* PMU init message received */
-#define PMU_STATE_ELPG_BOOTING          3 /* PMU is booting */
-#define PMU_STATE_ELPG_BOOTED           4 /* ELPG is initialized */
-#define PMU_STATE_LOADING_PG_BUF        5 /* Loading PG buf */
-#define PMU_STATE_LOADING_ZBC           6 /* Loading ZBC buf */
-#define PMU_STATE_STARTED               7 /* Fully unitialized */
-#define PMU_STATE_EXIT                  8 /* Exit PMU state machine */
-
-struct nvgpu_pg_init {
-        bool state_change;
-        struct nvgpu_cond wq;
-        struct nvgpu_thread state_task;
-};
-
-struct pmu_gk20a {
-
-        union {
-                struct pmu_ucode_desc *desc;
-                struct pmu_ucode_desc_v1 *desc_v1;
-        };
-        struct nvgpu_mem ucode;
-
-        struct nvgpu_mem pg_buf;
-        /* TBD: remove this if ZBC seq is fixed */
-        struct nvgpu_mem seq_buf;
-        struct nvgpu_mem trace_buf;
-        struct nvgpu_mem wpr_buf;
-        bool buf_loaded;
-
-        struct pmu_sha1_gid gid_info;
-
-        struct pmu_queue queue[PMU_QUEUE_COUNT];
-
-        struct pmu_sequence *seq;
-        unsigned long pmu_seq_tbl[PMU_SEQ_TBL_SIZE];
-        u32 next_seq_desc;
-
-        struct pmu_mutex *mutex;
-        u32 mutex_cnt;
-
-        struct nvgpu_mutex pmu_copy_lock;
-        struct nvgpu_mutex pmu_seq_lock;
-
-        struct nvgpu_allocator dmem;
-
-        u32 *ucode_image;
-        bool pmu_ready;
-
-        u32 zbc_save_done;
-
-        u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE];
-
-        u32 elpg_stat;
-
-        u32 mscg_stat;
-        u32 mscg_transition_state;
-
-        int pmu_state;
-
-#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC        1 /* msec */
-        struct nvgpu_pg_init pg_init;
-        struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */
-        struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */
-        int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
-
-        union {
-                struct pmu_perfmon_counter_v2 perfmon_counter_v2;
-                struct pmu_perfmon_counter_v0 perfmon_counter_v0;
-        };
-        u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
-
-        bool initialized;
-
-        void (*remove_support)(struct pmu_gk20a *pmu);
-        bool sw_ready;
-        bool perfmon_ready;
-
-        u32 sample_buffer;
-        u32 load_shadow;
-        u32 load_avg;
-
-        struct nvgpu_mutex isr_mutex;
-        bool isr_enabled;
-
-        bool zbc_ready;
-        union {
-                struct pmu_cmdline_args_v0 args_v0;
-                struct pmu_cmdline_args_v1 args_v1;
-                struct pmu_cmdline_args_v2 args_v2;
-                struct pmu_cmdline_args_v3 args_v3;
-                struct pmu_cmdline_args_v4 args_v4;
-                struct pmu_cmdline_args_v5 args_v5;
-        };
-        unsigned long perfmon_events_cnt;
-        bool perfmon_sampling_enabled;
-        u8 pmu_mode; /*Added for GM20b, and ACR*/
-        u32 falcon_id;
-        u32 aelpg_param[5];
-        u32 override_done;
-
-        struct nvgpu_firmware *fw;
-};
-
 int gk20a_init_pmu_support(struct gk20a *g);
 int gk20a_init_pmu_bind_fecs(struct gk20a *g);
 
@@ -426,8 +138,8 @@ void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
 
 int gk20a_pmu_perfmon_enable(struct gk20a *g, bool enable);
 
-int pmu_mutex_acquire(struct pmu_gk20a *pmu, u32 id, u32 *token);
-int pmu_mutex_release(struct pmu_gk20a *pmu, u32 id, u32 *token);
+int pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
+int pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
 int gk20a_pmu_destroy(struct gk20a *g);
 int gk20a_pmu_load_norm(struct gk20a *g, u32 *load);
 int gk20a_pmu_load_update(struct gk20a *g);
@@ -436,33 +148,33 @@ void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
                 u32 *total_cycles);
 void gk20a_init_pmu_ops(struct gpu_ops *gops);
 
-void pmu_copy_to_dmem(struct pmu_gk20a *pmu,
+void pmu_copy_to_dmem(struct nvgpu_pmu *pmu,
                 u32 dst, u8 *src, u32 size, u8 port);
-void pmu_copy_from_dmem(struct pmu_gk20a *pmu,
+void pmu_copy_from_dmem(struct nvgpu_pmu *pmu,
                 u32 src, u8 *dst, u32 size, u8 port);
-int pmu_reset(struct pmu_gk20a *pmu);
-int pmu_bootstrap(struct pmu_gk20a *pmu);
-int gk20a_init_pmu(struct pmu_gk20a *pmu);
-void pmu_dump_falcon_stats(struct pmu_gk20a *pmu);
-void gk20a_remove_pmu_support(struct pmu_gk20a *pmu);
-void pmu_seq_init(struct pmu_gk20a *pmu);
+int pmu_reset(struct nvgpu_pmu *pmu);
+int pmu_bootstrap(struct nvgpu_pmu *pmu);
+int gk20a_init_pmu(struct nvgpu_pmu *pmu);
+void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
+void gk20a_remove_pmu_support(struct nvgpu_pmu *pmu);
+void pmu_seq_init(struct nvgpu_pmu *pmu);
 
-int gk20a_init_pmu(struct pmu_gk20a *pmu);
+int gk20a_init_pmu(struct nvgpu_pmu *pmu);
 
 int gk20a_pmu_ap_send_command(struct gk20a *g,
                 union pmu_ap_cmd *p_ap_cmd, bool b_block);
 int gk20a_aelpg_init(struct gk20a *g);
 int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
-void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable);
-int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout_ms,
+void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
+int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
                                  u32 *var, u32 val);
 void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
                                 void *param, u32 handle, u32 status);
 void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
                 struct pmu_pg_stats_data *pg_stat_data);
 int gk20a_pmu_reset(struct gk20a *g);
-int pmu_idle(struct pmu_gk20a *pmu);
-int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable);
+int pmu_idle(struct nvgpu_pmu *pmu);
+int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable);
 
 void gk20a_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem);
 void gk20a_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
@@ -475,7 +187,7 @@ int gk20a_pmu_get_pg_stats(struct gk20a *g,
                 u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data);
 bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
 
-int nvgpu_pmu_perfmon_start_sampling(struct pmu_gk20a *pmu);
-int nvgpu_pmu_perfmon_stop_sampling(struct pmu_gk20a *pmu);
+int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu);
+int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu);
 
 #endif /*__PMU_GK20A_H__*/