gpu: nvgpu: PMU debug reorg

- Moved PMU debug related code to pmu_debug.c
  Print pmu trace buffer
  Moved PMU controller/engine status dump debug code
  Moved ELPG stats  dump code
- Removed PMU falcon controller status dump code & used
nvgpu_flcn_dump_stats() method,
- Method to print ELPG stats.
- PMU HAL to print PMU engine & ELPG debug info upon error

NVGPU JIRA-96

Change-Id: Iaa3d983f1d3b78a1b051beb6c109d3da8f8c90bc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1516640
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 2 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 3ad0c116..3992b029 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -57,12 +57,10 @@ int gk20a_init_pmu_setup_hw1(struct gk20a *g);
 void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr);
 bool gk20a_is_pmu_supported(struct gk20a *g);
 
-void pmu_copy_to_dmem(struct nvgpu_pmu *pmu,
-                u32 dst, u8 *src, u32 size, u8 port);
 int pmu_bootstrap(struct nvgpu_pmu *pmu);
 
-void pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
-void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
+void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
+void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
 
 void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
 int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
@@ -74,8 +72,4 @@ void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
 bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
 int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
 
-int pmu_idle(struct nvgpu_pmu *pmu);
-
-bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
-
 #endif /*__PMU_GK20A_H__*/