gpu:nvgpu:gm20b: disable irqs when hs pmu executes

bug 200040021

polling halt irq to check for hs bin completion
keep irqs disabled to avoid executing irq handler

Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/554659
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 64b126f6..7a62f05c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -1048,7 +1048,7 @@ static int pmu_idle(struct pmu_gk20a *pmu)
         return 0;
 }
 
-static void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable)
+void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);