diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-11-14 00:57:38 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-17 11:15:12 -0500 |
commit | efe0758081f25b39d5bb8b097fc0ae64d0e47c3f (patch) | |
tree | f99d333adfb8db97524508d2b81beec1164e9fde /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | 157ff622f3156a68281a5d1c0eb97bc8ad3a5b3b (diff) |
gpu: nvgpu: fix pmu->mscg_stat optimization issue
- with help of WRITE_ONCE() & ACCESS_ONCE()
make sure variable pmu->mscg_stat read/write goes through
without optimization
- Added WRITE_ONCE() define for kernel-3.18 version & below
to support backward compatibility
issue: inconsistencies on getting MSCG to trigger consistently in P5
due to a lack of memory barrier around and volatile accesses to the
variable pmu->mscg_stat
JIRA DNVGPU-71
Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252524
(cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b)
Reviewed-on: http://git-master/r/1271614
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index ef6a5943..11baa7af 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -3388,7 +3388,9 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, | |||
3388 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) { | 3388 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED) { |
3389 | pmu->initialized = true; | 3389 | pmu->initialized = true; |
3390 | pmu->pmu_state = PMU_STATE_STARTED; | 3390 | pmu->pmu_state = PMU_STATE_STARTED; |
3391 | pmu->mscg_stat = PMU_MSCG_DISABLED; | 3391 | WRITE_ONCE(pmu->mscg_stat, PMU_MSCG_DISABLED); |
3392 | /* make status visible */ | ||
3393 | smp_mb(); | ||
3392 | } else { | 3394 | } else { |
3393 | pmu->pmu_state = PMU_STATE_ELPG_BOOTED; | 3395 | pmu->pmu_state = PMU_STATE_ELPG_BOOTED; |
3394 | schedule_work(&pmu->pg_init); | 3396 | schedule_work(&pmu->pg_init); |
@@ -4849,7 +4851,7 @@ int gk20a_pmu_enable_elpg(struct gk20a *g) | |||
4849 | pg_engine_id++) { | 4851 | pg_engine_id++) { |
4850 | 4852 | ||
4851 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS && | 4853 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS && |
4852 | pmu->mscg_stat == PMU_MSCG_DISABLED) | 4854 | ACCESS_ONCE(pmu->mscg_stat) == PMU_MSCG_DISABLED) |
4853 | continue; | 4855 | continue; |
4854 | 4856 | ||
4855 | if (BIT(pg_engine_id) & pg_engine_id_list) | 4857 | if (BIT(pg_engine_id) & pg_engine_id_list) |
@@ -4925,7 +4927,7 @@ int gk20a_pmu_disable_elpg(struct gk20a *g) | |||
4925 | pg_engine_id++) { | 4927 | pg_engine_id++) { |
4926 | 4928 | ||
4927 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS && | 4929 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS && |
4928 | pmu->mscg_stat == PMU_MSCG_DISABLED) | 4930 | ACCESS_ONCE(pmu->mscg_stat) == PMU_MSCG_DISABLED) |
4929 | continue; | 4931 | continue; |
4930 | 4932 | ||
4931 | if (BIT(pg_engine_id) & pg_engine_id_list) { | 4933 | if (BIT(pg_engine_id) & pg_engine_id_list) { |