diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-09-12 17:51:40 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 18:05:25 -0400 |
commit | e3ae03e17abd452c157545234348692364b4b9f6 (patch) | |
tree | 121b3dcde56c87f9a1008ad4f5effbeb69cff945 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | 78e3d22da3c2513d425c8c2560468ce854a982dd (diff) |
gpu: nvgpu: Add MC APIs for reset masks
Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.
JIRA NVGPU-954
Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f231e088..6eecc4fa 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <nvgpu/io.h> | 34 | #include <nvgpu/io.h> |
35 | #include <nvgpu/clk_arb.h> | 35 | #include <nvgpu/clk_arb.h> |
36 | #include <nvgpu/utils.h> | 36 | #include <nvgpu/utils.h> |
37 | #include <nvgpu/unit.h> | ||
37 | 38 | ||
38 | #include "gk20a.h" | 39 | #include "gk20a.h" |
39 | #include "gr_gk20a.h" | 40 | #include "gr_gk20a.h" |
@@ -497,24 +498,21 @@ void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
497 | 498 | ||
498 | bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) | 499 | bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) |
499 | { | 500 | { |
500 | u32 pmc_enable; | ||
501 | bool status = false; | 501 | bool status = false; |
502 | 502 | ||
503 | pmc_enable = gk20a_readl(g, mc_enable_r()); | 503 | status = g->ops.mc.is_enabled(g, NVGPU_UNIT_PWR); |
504 | if (mc_enable_pwr_v(pmc_enable) == | ||
505 | mc_enable_pwr_disabled_v()) { | ||
506 | status = true; | ||
507 | } | ||
508 | 504 | ||
509 | return status; | 505 | return status; |
510 | } | 506 | } |
511 | 507 | ||
512 | int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) | 508 | int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) |
513 | { | 509 | { |
510 | u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR); | ||
511 | |||
514 | if (do_reset) { | 512 | if (do_reset) { |
515 | g->ops.mc.enable(g, mc_enable_pwr_enabled_f()); | 513 | g->ops.mc.enable(g, reset_mask); |
516 | } else { | 514 | } else { |
517 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); | 515 | g->ops.mc.disable(g, reset_mask); |
518 | } | 516 | } |
519 | 517 | ||
520 | return 0; | 518 | return 0; |
@@ -659,8 +657,6 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) | |||
659 | pwr_falcon_exterrstat_valid_true_v()) { | 657 | pwr_falcon_exterrstat_valid_true_v()) { |
660 | nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x", | 658 | nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x", |
661 | gk20a_readl(g, pwr_falcon_exterraddr_r())); | 659 | gk20a_readl(g, pwr_falcon_exterraddr_r())); |
662 | nvgpu_err(g, "pmc_enable : 0x%x", | ||
663 | gk20a_readl(g, mc_enable_r())); | ||
664 | } | 660 | } |
665 | 661 | ||
666 | /* Print PMU F/W debug prints */ | 662 | /* Print PMU F/W debug prints */ |