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authorMahantesh Kumbar <mkumbar@nvidia.com>2015-09-21 18:02:37 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2015-09-30 11:29:13 -0400
commitdab594ac13e5ca76d09a9ab383c35ad67c1444ef (patch)
tree44098f9e26af1ba2f9812bcf16dabe8c6fd3ec8e /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
parentb1cd94025bcd51a82e15eb314ab30e4418372c7f (diff)
gpu: nvgpu: ELPG init & statistics update
- Required init param to start elpg - change in statistics dump Bug 1684939 Change-Id: I26dca52079f08b8962e9cb758831910207610220 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/802456 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/806179 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c29
1 files changed, 22 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 0328e100..4d459ef4 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2769,6 +2769,8 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
2769 gops->pmu.init_wpr_region = NULL; 2769 gops->pmu.init_wpr_region = NULL;
2770 gops->pmu.load_lsfalcon_ucode = NULL; 2770 gops->pmu.load_lsfalcon_ucode = NULL;
2771 gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; 2771 gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase;
2772 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics;
2773 gops->pmu.pmu_pg_grinit_param = NULL;
2772} 2774}
2773 2775
2774int gk20a_init_pmu_support(struct gk20a *g) 2776int gk20a_init_pmu_support(struct gk20a *g)
@@ -2884,6 +2886,10 @@ static int pmu_init_powergating(struct gk20a *g)
2884 2886
2885 gk20a_gr_wait_initialized(g); 2887 gk20a_gr_wait_initialized(g);
2886 2888
2889 if (g->ops.pmu.pmu_pg_grinit_param)
2890 g->ops.pmu.pmu_pg_grinit_param(g,
2891 PMU_PG_FEATURE_GR_POWER_GATING_ENABLED);
2892
2887 /* init ELPG */ 2893 /* init ELPG */
2888 memset(&cmd, 0, sizeof(struct pmu_cmd)); 2894 memset(&cmd, 0, sizeof(struct pmu_cmd));
2889 cmd.hdr.unit_id = PMU_UNIT_PG; 2895 cmd.hdr.unit_id = PMU_UNIT_PG;
@@ -4241,11 +4247,24 @@ void gk20a_pmu_reset_load_counters(struct gk20a *g)
4241 gk20a_idle(g->dev); 4247 gk20a_idle(g->dev);
4242} 4248}
4243 4249
4250void gk20a_pmu_elpg_statistics(struct gk20a *g,
4251 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt)
4252{
4253 struct pmu_gk20a *pmu = &g->pmu;
4254 struct pmu_pg_stats stats;
4255
4256 pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset,
4257 (u8 *)&stats, sizeof(struct pmu_pg_stats), 0);
4258
4259 *ingating_time = stats.pg_ingating_time_us;
4260 *ungating_time = stats.pg_ungating_time_us;
4261 *gating_cnt = stats.pg_gating_cnt;
4262}
4263
4244static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g, 4264static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g,
4245 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) 4265 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt)
4246{ 4266{
4247 struct pmu_gk20a *pmu = &g->pmu; 4267 struct pmu_gk20a *pmu = &g->pmu;
4248 struct pmu_pg_stats stats;
4249 4268
4250 if (!pmu->initialized) { 4269 if (!pmu->initialized) {
4251 *ingating_time = 0; 4270 *ingating_time = 0;
@@ -4254,12 +4273,8 @@ static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g,
4254 return 0; 4273 return 0;
4255 } 4274 }
4256 4275
4257 pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, 4276 g->ops.pmu.pmu_elpg_statistics(g, ingating_time,
4258 (u8 *)&stats, sizeof(struct pmu_pg_stats), 0); 4277 ungating_time, gating_cnt);
4259
4260 *ingating_time = stats.pg_ingating_time_us;
4261 *ungating_time = stats.pg_ungating_time_us;
4262 *gating_cnt = stats.pg_gating_cnt;
4263 4278
4264 return 0; 4279 return 0;
4265} 4280}