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authorSupriya <ssharatkumar@nvidia.com>2016-03-21 08:09:48 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-04-06 22:38:19 -0400
commitbf82cd220a1ea4f8e327bc9bae51e36669c43778 (patch)
tree6f44623e05efc4aab7654fb106dc3b82472863f6 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
parent135d6db448cfaf5a366e6572f1a02a67e35d70db (diff)
gpu: nvgpu: Add Fuse prints on PMU Halt
-Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: I59f5fcf4a69bdd2a2eea81a69dd99bb9c4c21e1d Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/1113464 (cherry picked from commit d0320eed72c5070c4fcc7564c02fa38599984751) Reviewed-on: http://git-master/r/1120429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 60c87979..4edfe90c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2772,6 +2772,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
2772 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; 2772 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics;
2773 gops->pmu.pmu_pg_grinit_param = NULL; 2773 gops->pmu.pmu_pg_grinit_param = NULL;
2774 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; 2774 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
2775 gops->pmu.dump_secure_fuses = NULL;
2775} 2776}
2776 2777
2777int gk20a_init_pmu_support(struct gk20a *g) 2778int gk20a_init_pmu_support(struct gk20a *g)
@@ -3730,6 +3731,11 @@ void gk20a_pmu_isr(struct gk20a *g)
3730 gk20a_err(dev_from_gk20a(g), 3731 gk20a_err(dev_from_gk20a(g),
3731 "pmu halt intr not implemented"); 3732 "pmu halt intr not implemented");
3732 pmu_dump_falcon_stats(pmu); 3733 pmu_dump_falcon_stats(pmu);
3734 if (gk20a_readl(g, pwr_pmu_mailbox_r
3735 (PMU_MODE_MISMATCH_STATUS_MAILBOX_R)) ==
3736 PMU_MODE_MISMATCH_STATUS_VAL)
3737 if (g->ops.pmu.dump_secure_fuses)
3738 g->ops.pmu.dump_secure_fuses(g);
3733 } 3739 }
3734 if (intr & pwr_falcon_irqstat_exterr_true_f()) { 3740 if (intr & pwr_falcon_irqstat_exterr_true_f()) {
3735 gk20a_err(dev_from_gk20a(g), 3741 gk20a_err(dev_from_gk20a(g),