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authorMahantesh Kumbar <mkumbar@nvidia.com>2015-04-07 05:57:24 -0400
committerIshan Mittal <imittal@nvidia.com>2015-05-18 02:01:38 -0400
commitae2a356f367eb399519d194a33aba6e0f83834a4 (patch)
tree35ae4da3b93b1bca042a21b50864023d6f073cbe /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
parent3090ace7937e38513c421426f1066836ef55877e (diff)
gpu: nvgpu: updated gpmu interface data struct.
- pmu version 19494277 is from CL 19495746 - updated gpmu interface data struct with respect to latest pmu ucode interface headers. gpmuifpg.h - 19199047 gpmuifperfmon.h - 18238819 gpmuifpmu.h - 19199047 gpmuifacr.h - 19343196 gpmuifcmn.h - 19264862 rmflcnbl.h - 19317152 Bug 200085428 Change-Id: I7db56dcf5a3038b40da37a69e8723a2e9a652e4b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/728461 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c412
1 files changed, 395 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 275fbd4e..6313b9d5 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -155,6 +155,39 @@ static void set_pmu_cmdline_args_falctracedmaidx_v2(
155 pmu->args_v2.falc_trace_dma_idx = idx; 155 pmu->args_v2.falc_trace_dma_idx = idx;
156} 156}
157 157
158
159static void set_pmu_cmdline_args_falctracedmabase_v4(struct pmu_gk20a *pmu)
160{
161 pmu->args_v4.dma_addr.dma_base = ((u32)pmu->trace_buf.gpu_va)/0x100;
162 pmu->args_v4.dma_addr.dma_base1 = 0;
163 pmu->args_v4.dma_addr.dma_offset = 0;
164}
165
166static u32 pmu_cmdline_size_v4(struct pmu_gk20a *pmu)
167{
168 return sizeof(struct pmu_cmdline_args_v4);
169}
170
171static void set_pmu_cmdline_args_cpufreq_v4(struct pmu_gk20a *pmu, u32 freq)
172{
173 pmu->args_v4.cpu_freq_hz = freq;
174}
175static void set_pmu_cmdline_args_secure_mode_v4(struct pmu_gk20a *pmu, u32 val)
176{
177 pmu->args_v4.secure_mode = val;
178}
179
180static void set_pmu_cmdline_args_falctracesize_v4(
181 struct pmu_gk20a *pmu, u32 size)
182{
183 pmu->args_v4.falc_trace_size = size;
184}
185static void set_pmu_cmdline_args_falctracedmaidx_v4(
186 struct pmu_gk20a *pmu, u32 idx)
187{
188 pmu->args_v4.falc_trace_dma_idx = idx;
189}
190
158static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu) 191static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu)
159{ 192{
160 return sizeof(struct pmu_cmdline_args_v3); 193 return sizeof(struct pmu_cmdline_args_v3);
@@ -263,6 +296,11 @@ static void set_pmu_cmdline_args_cpufreq_v0(struct pmu_gk20a *pmu, u32 freq)
263 pmu->args_v0.cpu_freq_hz = freq; 296 pmu->args_v0.cpu_freq_hz = freq;
264} 297}
265 298
299static void *get_pmu_cmdline_args_ptr_v4(struct pmu_gk20a *pmu)
300{
301 return (void *)(&pmu->args_v4);
302}
303
266static void *get_pmu_cmdline_args_ptr_v3(struct pmu_gk20a *pmu) 304static void *get_pmu_cmdline_args_ptr_v3(struct pmu_gk20a *pmu)
267{ 305{
268 return (void *)(&pmu->args_v3); 306 return (void *)(&pmu->args_v3);
@@ -283,6 +321,11 @@ static void *get_pmu_cmdline_args_ptr_v0(struct pmu_gk20a *pmu)
283 return (void *)(&pmu->args_v0); 321 return (void *)(&pmu->args_v0);
284} 322}
285 323
324static u32 get_pmu_allocation_size_v2(struct pmu_gk20a *pmu)
325{
326 return sizeof(struct pmu_allocation_v2);
327}
328
286static u32 get_pmu_allocation_size_v1(struct pmu_gk20a *pmu) 329static u32 get_pmu_allocation_size_v1(struct pmu_gk20a *pmu)
287{ 330{
288 return sizeof(struct pmu_allocation_v1); 331 return sizeof(struct pmu_allocation_v1);
@@ -293,6 +336,14 @@ static u32 get_pmu_allocation_size_v0(struct pmu_gk20a *pmu)
293 return sizeof(struct pmu_allocation_v0); 336 return sizeof(struct pmu_allocation_v0);
294} 337}
295 338
339static void set_pmu_allocation_ptr_v2(struct pmu_gk20a *pmu,
340 void **pmu_alloc_ptr, void *assign_ptr)
341{
342 struct pmu_allocation_v2 **pmu_a_ptr =
343 (struct pmu_allocation_v2 **)pmu_alloc_ptr;
344 *pmu_a_ptr = (struct pmu_allocation_v2 *)assign_ptr;
345}
346
296static void set_pmu_allocation_ptr_v1(struct pmu_gk20a *pmu, 347static void set_pmu_allocation_ptr_v1(struct pmu_gk20a *pmu,
297 void **pmu_alloc_ptr, void *assign_ptr) 348 void **pmu_alloc_ptr, void *assign_ptr)
298{ 349{
@@ -309,6 +360,14 @@ static void set_pmu_allocation_ptr_v0(struct pmu_gk20a *pmu,
309 *pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr; 360 *pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr;
310} 361}
311 362
363static void pmu_allocation_set_dmem_size_v2(struct pmu_gk20a *pmu,
364 void *pmu_alloc_ptr, u16 size)
365{
366 struct pmu_allocation_v2 *pmu_a_ptr =
367 (struct pmu_allocation_v2 *)pmu_alloc_ptr;
368 pmu_a_ptr->alloc.dmem.size = size;
369}
370
312static void pmu_allocation_set_dmem_size_v1(struct pmu_gk20a *pmu, 371static void pmu_allocation_set_dmem_size_v1(struct pmu_gk20a *pmu,
313 void *pmu_alloc_ptr, u16 size) 372 void *pmu_alloc_ptr, u16 size)
314{ 373{
@@ -325,6 +384,14 @@ static void pmu_allocation_set_dmem_size_v0(struct pmu_gk20a *pmu,
325 pmu_a_ptr->alloc.dmem.size = size; 384 pmu_a_ptr->alloc.dmem.size = size;
326} 385}
327 386
387static u16 pmu_allocation_get_dmem_size_v2(struct pmu_gk20a *pmu,
388 void *pmu_alloc_ptr)
389{
390 struct pmu_allocation_v2 *pmu_a_ptr =
391 (struct pmu_allocation_v2 *)pmu_alloc_ptr;
392 return pmu_a_ptr->alloc.dmem.size;
393}
394
328static u16 pmu_allocation_get_dmem_size_v1(struct pmu_gk20a *pmu, 395static u16 pmu_allocation_get_dmem_size_v1(struct pmu_gk20a *pmu,
329 void *pmu_alloc_ptr) 396 void *pmu_alloc_ptr)
330{ 397{
@@ -341,6 +408,14 @@ static u16 pmu_allocation_get_dmem_size_v0(struct pmu_gk20a *pmu,
341 return pmu_a_ptr->alloc.dmem.size; 408 return pmu_a_ptr->alloc.dmem.size;
342} 409}
343 410
411static u32 pmu_allocation_get_dmem_offset_v2(struct pmu_gk20a *pmu,
412 void *pmu_alloc_ptr)
413{
414 struct pmu_allocation_v2 *pmu_a_ptr =
415 (struct pmu_allocation_v2 *)pmu_alloc_ptr;
416 return pmu_a_ptr->alloc.dmem.offset;
417}
418
344static u32 pmu_allocation_get_dmem_offset_v1(struct pmu_gk20a *pmu, 419static u32 pmu_allocation_get_dmem_offset_v1(struct pmu_gk20a *pmu,
345 void *pmu_alloc_ptr) 420 void *pmu_alloc_ptr)
346{ 421{
@@ -357,6 +432,14 @@ static u32 pmu_allocation_get_dmem_offset_v0(struct pmu_gk20a *pmu,
357 return pmu_a_ptr->alloc.dmem.offset; 432 return pmu_a_ptr->alloc.dmem.offset;
358} 433}
359 434
435static u32 *pmu_allocation_get_dmem_offset_addr_v2(struct pmu_gk20a *pmu,
436 void *pmu_alloc_ptr)
437{
438 struct pmu_allocation_v2 *pmu_a_ptr =
439 (struct pmu_allocation_v2 *)pmu_alloc_ptr;
440 return &pmu_a_ptr->alloc.dmem.offset;
441}
442
360static u32 *pmu_allocation_get_dmem_offset_addr_v1(struct pmu_gk20a *pmu, 443static u32 *pmu_allocation_get_dmem_offset_addr_v1(struct pmu_gk20a *pmu,
361 void *pmu_alloc_ptr) 444 void *pmu_alloc_ptr)
362{ 445{
@@ -373,6 +456,14 @@ static u32 *pmu_allocation_get_dmem_offset_addr_v0(struct pmu_gk20a *pmu,
373 return &pmu_a_ptr->alloc.dmem.offset; 456 return &pmu_a_ptr->alloc.dmem.offset;
374} 457}
375 458
459static void pmu_allocation_set_dmem_offset_v2(struct pmu_gk20a *pmu,
460 void *pmu_alloc_ptr, u32 offset)
461{
462 struct pmu_allocation_v2 *pmu_a_ptr =
463 (struct pmu_allocation_v2 *)pmu_alloc_ptr;
464 pmu_a_ptr->alloc.dmem.offset = offset;
465}
466
376static void pmu_allocation_set_dmem_offset_v1(struct pmu_gk20a *pmu, 467static void pmu_allocation_set_dmem_offset_v1(struct pmu_gk20a *pmu,
377 void *pmu_alloc_ptr, u32 offset) 468 void *pmu_alloc_ptr, u32 offset)
378{ 469{
@@ -687,6 +778,105 @@ static void *get_pmu_sequence_out_alloc_ptr_v0(struct pmu_sequence *seq)
687 return (void *)(&seq->out_v0); 778 return (void *)(&seq->out_v0);
688} 779}
689 780
781static u8 pg_cmd_eng_buf_load_size_v0(struct pmu_pg_cmd *pg)
782{
783 return sizeof(pg->eng_buf_load_v0);
784}
785
786static u8 pg_cmd_eng_buf_load_size_v1(struct pmu_pg_cmd *pg)
787{
788 return sizeof(pg->eng_buf_load_v1);
789}
790
791static void pg_cmd_eng_buf_load_set_cmd_type_v0(struct pmu_pg_cmd *pg,
792 u8 value)
793{
794 pg->eng_buf_load_v0.cmd_type = value;
795}
796
797static void pg_cmd_eng_buf_load_set_cmd_type_v1(struct pmu_pg_cmd *pg,
798 u8 value)
799{
800 pg->eng_buf_load_v1.cmd_type = value;
801}
802static void pg_cmd_eng_buf_load_set_engine_id_v0(struct pmu_pg_cmd *pg,
803 u8 value)
804{
805 pg->eng_buf_load_v0.engine_id = value;
806}
807static void pg_cmd_eng_buf_load_set_engine_id_v1(struct pmu_pg_cmd *pg,
808 u8 value)
809{
810 pg->eng_buf_load_v1.engine_id = value;
811}
812static void pg_cmd_eng_buf_load_set_buf_idx_v0(struct pmu_pg_cmd *pg,
813 u8 value)
814{
815 pg->eng_buf_load_v0.buf_idx = value;
816}
817static void pg_cmd_eng_buf_load_set_buf_idx_v1(struct pmu_pg_cmd *pg,
818 u8 value)
819{
820 pg->eng_buf_load_v1.buf_idx = value;
821}
822
823static void pg_cmd_eng_buf_load_set_pad_v0(struct pmu_pg_cmd *pg,
824 u8 value)
825{
826 pg->eng_buf_load_v0.pad = value;
827}
828static void pg_cmd_eng_buf_load_set_pad_v1(struct pmu_pg_cmd *pg,
829 u8 value)
830{
831 pg->eng_buf_load_v1.pad = value;
832}
833
834static void pg_cmd_eng_buf_load_set_buf_size_v0(struct pmu_pg_cmd *pg,
835 u16 value)
836{
837 pg->eng_buf_load_v0.buf_size = value;
838}
839static void pg_cmd_eng_buf_load_set_buf_size_v1(struct pmu_pg_cmd *pg,
840 u16 value)
841{
842 pg->eng_buf_load_v1.buf_size = value;
843}
844
845static void pg_cmd_eng_buf_load_set_dma_base_v0(struct pmu_pg_cmd *pg,
846 u32 value)
847{
848 pg->eng_buf_load_v0.dma_base = value;
849}
850static void pg_cmd_eng_buf_load_set_dma_base_v1(struct pmu_pg_cmd *pg,
851 u32 value)
852{
853 pg->eng_buf_load_v1.dma_addr.dma_base = value;
854 pg->eng_buf_load_v1.dma_addr.dma_base1 = 0;
855}
856
857static void pg_cmd_eng_buf_load_set_dma_offset_v0(struct pmu_pg_cmd *pg,
858 u8 value)
859{
860 pg->eng_buf_load_v0.dma_offset = value;
861}
862static void pg_cmd_eng_buf_load_set_dma_offset_v1(struct pmu_pg_cmd *pg,
863 u8 value)
864{
865 pg->eng_buf_load_v1.dma_addr.dma_offset = value;
866}
867
868static void pg_cmd_eng_buf_load_set_dma_idx_v0(struct pmu_pg_cmd *pg,
869 u8 value)
870{
871 pg->eng_buf_load_v0.dma_idx = value;
872}
873static void pg_cmd_eng_buf_load_set_dma_idx_v1(struct pmu_pg_cmd *pg,
874 u8 value)
875{
876 pg->eng_buf_load_v1.dma_idx = value;
877}
878
879
690int gk20a_init_pmu(struct pmu_gk20a *pmu) 880int gk20a_init_pmu(struct pmu_gk20a *pmu)
691{ 881{
692 struct gk20a *g = gk20a_from_pmu(pmu); 882 struct gk20a *g = gk20a_from_pmu(pmu);
@@ -700,8 +890,126 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
700 pmu->remove_support = gk20a_remove_pmu_support; 890 pmu->remove_support = gk20a_remove_pmu_support;
701 891
702 switch (pmu->desc->app_version) { 892 switch (pmu->desc->app_version) {
703 case APP_VERSION: 893 case APP_VERSION_T186_0:
894 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
895 pg_cmd_eng_buf_load_size_v1;
896 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
897 pg_cmd_eng_buf_load_set_cmd_type_v1;
898 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
899 pg_cmd_eng_buf_load_set_engine_id_v1;
900 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
901 pg_cmd_eng_buf_load_set_buf_idx_v1;
902 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
903 pg_cmd_eng_buf_load_set_pad_v1;
904 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
905 pg_cmd_eng_buf_load_set_buf_size_v1;
906 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
907 pg_cmd_eng_buf_load_set_dma_base_v1;
908 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
909 pg_cmd_eng_buf_load_set_dma_offset_v1;
910 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
911 pg_cmd_eng_buf_load_set_dma_idx_v1;
912 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
913 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
914 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
915 g->ops.pmu_ver.set_perfmon_cntr_valid =
916 set_perfmon_cntr_valid_v2;
917 g->ops.pmu_ver.set_perfmon_cntr_index =
918 set_perfmon_cntr_index_v2;
919 g->ops.pmu_ver.set_perfmon_cntr_group_id =
920 set_perfmon_cntr_group_id_v2;
921 g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
922 g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
923 g->ops.pmu_ver.get_pmu_cmdline_args_size =
924 pmu_cmdline_size_v4;
925 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
926 set_pmu_cmdline_args_cpufreq_v4;
927 g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
928 set_pmu_cmdline_args_secure_mode_v4;
929 g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
930 set_pmu_cmdline_args_falctracesize_v4;
931 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
932 set_pmu_cmdline_args_falctracedmabase_v4;
933 g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
934 set_pmu_cmdline_args_falctracedmaidx_v4;
935 g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
936 get_pmu_cmdline_args_ptr_v4;
937 g->ops.pmu_ver.get_pmu_allocation_struct_size =
938 get_pmu_allocation_size_v2;
939 g->ops.pmu_ver.set_pmu_allocation_ptr =
940 set_pmu_allocation_ptr_v2;
941 g->ops.pmu_ver.pmu_allocation_set_dmem_size =
942 pmu_allocation_set_dmem_size_v2;
943 g->ops.pmu_ver.pmu_allocation_get_dmem_size =
944 pmu_allocation_get_dmem_size_v2;
945 g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
946 pmu_allocation_get_dmem_offset_v2;
947 g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
948 pmu_allocation_get_dmem_offset_addr_v2;
949 g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
950 pmu_allocation_set_dmem_offset_v2;
951 g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
952 get_pmu_init_msg_pmu_queue_params_v1;
953 g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
954 get_pmu_msg_pmu_init_msg_ptr_v1;
955 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
956 get_pmu_init_msg_pmu_sw_mg_off_v1;
957 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
958 get_pmu_init_msg_pmu_sw_mg_size_v1;
959 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
960 get_pmu_perfmon_cmd_start_size_v1;
961 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
962 get_perfmon_cmd_start_offsetofvar_v1;
963 g->ops.pmu_ver.perfmon_start_set_cmd_type =
964 perfmon_start_set_cmd_type_v1;
965 g->ops.pmu_ver.perfmon_start_set_group_id =
966 perfmon_start_set_group_id_v1;
967 g->ops.pmu_ver.perfmon_start_set_state_id =
968 perfmon_start_set_state_id_v1;
969 g->ops.pmu_ver.perfmon_start_set_flags =
970 perfmon_start_set_flags_v1;
971 g->ops.pmu_ver.perfmon_start_get_flags =
972 perfmon_start_get_flags_v1;
973 g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
974 get_pmu_perfmon_cmd_init_size_v1;
975 g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
976 get_perfmon_cmd_init_offsetofvar_v1;
977 g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
978 perfmon_cmd_init_set_sample_buffer_v1;
979 g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
980 perfmon_cmd_init_set_dec_cnt_v1;
981 g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
982 perfmon_cmd_init_set_base_cnt_id_v1;
983 g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
984 perfmon_cmd_init_set_samp_period_us_v1;
985 g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
986 perfmon_cmd_init_set_num_cnt_v1;
987 g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
988 perfmon_cmd_init_set_mov_avg_v1;
989 g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
990 get_pmu_sequence_in_alloc_ptr_v1;
991 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
992 get_pmu_sequence_out_alloc_ptr_v1;
993 break;
704 case APP_VERSION_GM20B_4: 994 case APP_VERSION_GM20B_4:
995 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
996 pg_cmd_eng_buf_load_size_v0;
997 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
998 pg_cmd_eng_buf_load_set_cmd_type_v0;
999 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
1000 pg_cmd_eng_buf_load_set_engine_id_v0;
1001 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
1002 pg_cmd_eng_buf_load_set_buf_idx_v0;
1003 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
1004 pg_cmd_eng_buf_load_set_pad_v0;
1005 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
1006 pg_cmd_eng_buf_load_set_buf_size_v0;
1007 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
1008 pg_cmd_eng_buf_load_set_dma_base_v0;
1009 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
1010 pg_cmd_eng_buf_load_set_dma_offset_v0;
1011 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
1012 pg_cmd_eng_buf_load_set_dma_idx_v0;
705 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; 1013 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
706 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2; 1014 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
707 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2; 1015 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
@@ -786,6 +1094,24 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
786 break; 1094 break;
787 case APP_VERSION_GM20B_3: 1095 case APP_VERSION_GM20B_3:
788 case APP_VERSION_GM20B_2: 1096 case APP_VERSION_GM20B_2:
1097 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1098 pg_cmd_eng_buf_load_size_v0;
1099 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
1100 pg_cmd_eng_buf_load_set_cmd_type_v0;
1101 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
1102 pg_cmd_eng_buf_load_set_engine_id_v0;
1103 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
1104 pg_cmd_eng_buf_load_set_buf_idx_v0;
1105 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
1106 pg_cmd_eng_buf_load_set_pad_v0;
1107 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
1108 pg_cmd_eng_buf_load_set_buf_size_v0;
1109 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
1110 pg_cmd_eng_buf_load_set_dma_base_v0;
1111 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
1112 pg_cmd_eng_buf_load_set_dma_offset_v0;
1113 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
1114 pg_cmd_eng_buf_load_set_dma_idx_v0;
789 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; 1115 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
790 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2; 1116 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
791 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2; 1117 g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
@@ -872,6 +1198,24 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
872 case APP_VERSION_GM20B: 1198 case APP_VERSION_GM20B:
873 case APP_VERSION_1: 1199 case APP_VERSION_1:
874 case APP_VERSION_2: 1200 case APP_VERSION_2:
1201 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1202 pg_cmd_eng_buf_load_size_v0;
1203 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
1204 pg_cmd_eng_buf_load_set_cmd_type_v0;
1205 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
1206 pg_cmd_eng_buf_load_set_engine_id_v0;
1207 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
1208 pg_cmd_eng_buf_load_set_buf_idx_v0;
1209 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
1210 pg_cmd_eng_buf_load_set_pad_v0;
1211 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
1212 pg_cmd_eng_buf_load_set_buf_size_v0;
1213 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
1214 pg_cmd_eng_buf_load_set_dma_base_v0;
1215 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
1216 pg_cmd_eng_buf_load_set_dma_offset_v0;
1217 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
1218 pg_cmd_eng_buf_load_set_dma_idx_v0;
875 g->ops.pmu_ver.cmd_id_zbc_table_update = 16; 1219 g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
876 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; 1220 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
877 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; 1221 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
@@ -955,6 +1299,24 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
955 get_pmu_sequence_out_alloc_ptr_v1; 1299 get_pmu_sequence_out_alloc_ptr_v1;
956 break; 1300 break;
957 case APP_VERSION_0: 1301 case APP_VERSION_0:
1302 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
1303 pg_cmd_eng_buf_load_size_v0;
1304 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
1305 pg_cmd_eng_buf_load_set_cmd_type_v0;
1306 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
1307 pg_cmd_eng_buf_load_set_engine_id_v0;
1308 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
1309 pg_cmd_eng_buf_load_set_buf_idx_v0;
1310 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
1311 pg_cmd_eng_buf_load_set_pad_v0;
1312 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
1313 pg_cmd_eng_buf_load_set_buf_size_v0;
1314 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
1315 pg_cmd_eng_buf_load_set_dma_base_v0;
1316 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
1317 pg_cmd_eng_buf_load_set_dma_offset_v0;
1318 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
1319 pg_cmd_eng_buf_load_set_dma_idx_v0;
958 g->ops.pmu_ver.cmd_id_zbc_table_update = 14; 1320 g->ops.pmu_ver.cmd_id_zbc_table_update = 14;
959 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; 1321 g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
960 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; 1322 g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
@@ -2187,14 +2549,22 @@ int gk20a_init_pmu_bind_fecs(struct gk20a *g)
2187 2549
2188 memset(&cmd, 0, sizeof(struct pmu_cmd)); 2550 memset(&cmd, 0, sizeof(struct pmu_cmd));
2189 cmd.hdr.unit_id = PMU_UNIT_PG; 2551 cmd.hdr.unit_id = PMU_UNIT_PG;
2190 cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_pg_cmd_eng_buf_load); 2552 cmd.hdr.size = PMU_CMD_HDR_SIZE +
2191 cmd.cmd.pg.eng_buf_load.cmd_type = PMU_PG_CMD_ID_ENG_BUF_LOAD; 2553 g->ops.pmu_ver.pg_cmd_eng_buf_load_size(&cmd.cmd.pg);
2192 cmd.cmd.pg.eng_buf_load.engine_id = ENGINE_GR_GK20A; 2554 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type(&cmd.cmd.pg,
2193 cmd.cmd.pg.eng_buf_load.buf_idx = PMU_PGENG_GR_BUFFER_IDX_FECS; 2555 PMU_PG_CMD_ID_ENG_BUF_LOAD);
2194 cmd.cmd.pg.eng_buf_load.buf_size = pmu->pg_buf.size; 2556 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id(&cmd.cmd.pg,
2195 cmd.cmd.pg.eng_buf_load.dma_base = u64_lo32(pmu->pg_buf.gpu_va >> 8); 2557 ENGINE_GR_GK20A);
2196 cmd.cmd.pg.eng_buf_load.dma_offset = (u8)(pmu->pg_buf.gpu_va & 0xFF); 2558 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx(&cmd.cmd.pg,
2197 cmd.cmd.pg.eng_buf_load.dma_idx = PMU_DMAIDX_VIRT; 2559 PMU_PGENG_GR_BUFFER_IDX_FECS);
2560 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg,
2561 pmu->pg_buf.size);
2562 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg,
2563 u64_lo32(pmu->pg_buf.gpu_va >> 8));
2564 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg,
2565 (u8)(pmu->pg_buf.gpu_va & 0xFF));
2566 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg,
2567 PMU_DMAIDX_VIRT);
2198 2568
2199 pmu->buf_loaded = false; 2569 pmu->buf_loaded = false;
2200 gk20a_dbg_pmu("cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS"); 2570 gk20a_dbg_pmu("cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS");
@@ -2212,14 +2582,22 @@ static void pmu_setup_hw_load_zbc(struct gk20a *g)
2212 2582
2213 memset(&cmd, 0, sizeof(struct pmu_cmd)); 2583 memset(&cmd, 0, sizeof(struct pmu_cmd));
2214 cmd.hdr.unit_id = PMU_UNIT_PG; 2584 cmd.hdr.unit_id = PMU_UNIT_PG;
2215 cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_pg_cmd_eng_buf_load); 2585 cmd.hdr.size = PMU_CMD_HDR_SIZE +
2216 cmd.cmd.pg.eng_buf_load.cmd_type = PMU_PG_CMD_ID_ENG_BUF_LOAD; 2586 g->ops.pmu_ver.pg_cmd_eng_buf_load_size(&cmd.cmd.pg);
2217 cmd.cmd.pg.eng_buf_load.engine_id = ENGINE_GR_GK20A; 2587 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type(&cmd.cmd.pg,
2218 cmd.cmd.pg.eng_buf_load.buf_idx = PMU_PGENG_GR_BUFFER_IDX_ZBC; 2588 PMU_PG_CMD_ID_ENG_BUF_LOAD);
2219 cmd.cmd.pg.eng_buf_load.buf_size = pmu->seq_buf.size; 2589 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id(&cmd.cmd.pg,
2220 cmd.cmd.pg.eng_buf_load.dma_base = u64_lo32(pmu->seq_buf.gpu_va >> 8); 2590 ENGINE_GR_GK20A);
2221 cmd.cmd.pg.eng_buf_load.dma_offset = (u8)(pmu->seq_buf.gpu_va & 0xFF); 2591 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx(&cmd.cmd.pg,
2222 cmd.cmd.pg.eng_buf_load.dma_idx = PMU_DMAIDX_VIRT; 2592 PMU_PGENG_GR_BUFFER_IDX_ZBC);
2593 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size(&cmd.cmd.pg,
2594 pmu->seq_buf.size);
2595 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg,
2596 u64_lo32(pmu->seq_buf.gpu_va >> 8));
2597 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg,
2598 (u8)(pmu->seq_buf.gpu_va & 0xFF));
2599 g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg,
2600 PMU_DMAIDX_VIRT);
2223 2601
2224 pmu->buf_loaded = false; 2602 pmu->buf_loaded = false;
2225 gk20a_dbg_pmu("cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC"); 2603 gk20a_dbg_pmu("cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC");
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:17:45 -0400