diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-09-10 11:41:49 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-24 11:12:03 -0400 |
commit | 863b47064445b3dd5cdc354821c8d3d14deade33 (patch) | |
tree | 1e53f26c1549d1970d752f74ab82a4d55642620b /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | fdf77eda18b59c305d4dd8436d8b09d42ec4718a (diff) |
gpu: nvgpu: PMU init sequence change
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
for PMU RTOS & does start PMU RTOS in secure & non-secure
based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
secured_pmu_start assignment for gp106 & gv100 to support
modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
to handle non secure PMU bootstrap, reused this method
for need chips.
JIRA NVGPU-1146
Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 86cb04d9..f231e088 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -490,40 +490,6 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set) | |||
490 | } | 490 | } |
491 | } | 491 | } |
492 | 492 | ||
493 | int gk20a_init_pmu_setup_hw1(struct gk20a *g) | ||
494 | { | ||
495 | struct nvgpu_pmu *pmu = &g->pmu; | ||
496 | int err = 0; | ||
497 | |||
498 | nvgpu_log_fn(g, " "); | ||
499 | |||
500 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
501 | nvgpu_flcn_reset(pmu->flcn); | ||
502 | pmu->isr_enabled = true; | ||
503 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
504 | |||
505 | /* setup apertures - virtual */ | ||
506 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
507 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
508 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
509 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
510 | /* setup apertures - physical */ | ||
511 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
512 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
513 | pwr_fbif_transcfg_target_local_fb_f()); | ||
514 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
515 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
516 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
517 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
518 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
519 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
520 | |||
521 | err = g->ops.pmu.pmu_nsbootstrap(pmu); | ||
522 | |||
523 | return err; | ||
524 | |||
525 | } | ||
526 | |||
527 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | 493 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) |
528 | { | 494 | { |
529 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); | 495 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); |