diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-02-02 16:24:21 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-16 14:48:29 -0400 |
commit | 589d6385b19a357cf566b75ded9355f9b8053ad7 (patch) | |
tree | 6453c1d3525c6a53b7b749a39b51e4a598680a64 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | 686c3b701fb1db75a0b416a25c288c04a396df31 (diff) |
gpu: nvgpu: Implement get_rate/set_rate as GPU op
Move clock APIs from gk20a_platform to gpu_ops. At the same time
allow use of internal get_rate/set_rate for querying both GPCCLK
and PWRCLK on iGPU.
At the same time we can replace calls to clk framework with the
new HAL and drop direct dependency to clk framework.
gp10b ops were replaced as a whole at HAL initialization. That
replaces anything set in platform probe stage, so reduce that to
touch only clock gating regs.
Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300113
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 7e37762c..c7e68f44 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -18,7 +18,6 @@ | |||
18 | 18 | ||
19 | #include <linux/delay.h> /* for mdelay */ | 19 | #include <linux/delay.h> /* for mdelay */ |
20 | #include <linux/firmware.h> | 20 | #include <linux/firmware.h> |
21 | #include <linux/clk.h> | ||
22 | #include <linux/module.h> | 21 | #include <linux/module.h> |
23 | #include <linux/debugfs.h> | 22 | #include <linux/debugfs.h> |
24 | #include <linux/dma-mapping.h> | 23 | #include <linux/dma-mapping.h> |
@@ -2474,7 +2473,6 @@ int pmu_reset(struct pmu_gk20a *pmu) | |||
2474 | int pmu_bootstrap(struct pmu_gk20a *pmu) | 2473 | int pmu_bootstrap(struct pmu_gk20a *pmu) |
2475 | { | 2474 | { |
2476 | struct gk20a *g = gk20a_from_pmu(pmu); | 2475 | struct gk20a *g = gk20a_from_pmu(pmu); |
2477 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
2478 | struct mm_gk20a *mm = &g->mm; | 2476 | struct mm_gk20a *mm = &g->mm; |
2479 | struct pmu_ucode_desc *desc = pmu->desc; | 2477 | struct pmu_ucode_desc *desc = pmu->desc; |
2480 | u64 addr_code, addr_data, addr_load; | 2478 | u64 addr_code, addr_data, addr_load; |
@@ -2499,7 +2497,7 @@ int pmu_bootstrap(struct pmu_gk20a *pmu) | |||
2499 | pmu, GK20A_PMU_DMAIDX_VIRT); | 2497 | pmu, GK20A_PMU_DMAIDX_VIRT); |
2500 | 2498 | ||
2501 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | 2499 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, |
2502 | clk_get_rate(platform->clk[1])); | 2500 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); |
2503 | 2501 | ||
2504 | addr_args = (pwr_falcon_hwcfg_dmem_size_v( | 2502 | addr_args = (pwr_falcon_hwcfg_dmem_size_v( |
2505 | gk20a_readl(g, pwr_falcon_hwcfg_r())) | 2503 | gk20a_readl(g, pwr_falcon_hwcfg_r())) |